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[142.162.112.119]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cda21100cfsm239690985a.24.2026.03.11.17.35.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 17:35:45 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1w0U1g-00000006a0E-4BUf; Wed, 11 Mar 2026 21:35:45 -0300 Date: Wed, 11 Mar 2026 21:35:44 -0300 From: Jason Gunthorpe To: Praveen Kannoju Cc: "saeedm@nvidia.com" , "leon@kernel.org" , "tariqt@nvidia.com" , "mbloch@nvidia.com" , "andrew+netdev@lunn.ch" , "davem@davemloft.net" , "edumazet@google.com" , "kuba@kernel.org" , "pabeni@redhat.com" , "netdev@vger.kernel.org" , "linux-rdma@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Rama Nichanamatlu , Manjunath Patil , Anand Khoje Subject: Re: [PATCH] net/mlx5: poll mlx5 eq during irq migration Message-ID: <20260312003544.GB1469476@ziepe.ca> References: <20260304161704.910564-1-praveen.kannoju@oracle.com> <20260304201151.GI964116@ziepe.ca> <20260306003217.GB1687929@ziepe.ca> <20260306231024.GF1687929@ziepe.ca> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Sat, Mar 07, 2026 at 05:43:56AM +0000, Praveen Kannoju wrote: > It had been very challenging to arrive at the cause. > we went thru many live debug sessions with Nvidia R&D team. > but we couldn't root cause. This tells why we eventually. > arrived at this mitigation as this issue is wide spread > and has been hurting many and many customers in cloud. It is almost certainly a qemu bug. If you cannot find it, then I suggest you work around it by having qemu inject a spurious interrupt around the migration situations. But make sure you have the already known qemu and kernel bug fixes for lost interrupts on MSI-X writes... Jason