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Sun, 15 Mar 2026 13:45:11 -0700 (PDT) Received: from nas.local ([2001:912:1ac0:1e00:c662:37ff:fe09:93df]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485563f8c23sm132043885e9.1.2026.03.15.13.45.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Mar 2026 13:45:10 -0700 (PDT) From: Damien Dejean To: andrew@lunn.ch, krzk+dt@kernel.org, robh@kernel.org, kuba@kernel.org, maxime.chevallier@bootlin.com, pabeni@redhat.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, edumazet@google.com, davem@davemloft.net, hkallweit1@gmail.com, Damien Dejean Subject: [PATCH net-next v8 2/4] net: phy: realtek: add RTL8224 pair order support Date: Sun, 15 Mar 2026 21:44:52 +0100 Message-ID: <20260315204454.124544-3-dam.dejean@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260315204454.124544-1-dam.dejean@gmail.com> References: <20260315204454.124544-1-dam.dejean@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The RTL8224 has a register to configure a pair swap (from ABCD order to DCBA) providing PCB designers more flexbility when wiring the chip. The swap parameter has to be set correctly for each of the 4 ports before the chip can detect a link. After a reset, this register is (unfortunately) left in a random state, thus it has to be initialized. On most of the devices the bootloader does it once for all and we can rely on the value set, on some other it is not and the kernel has to do it. The MDI pair swap can be set in the device tree using the property enet-phy-pair-order. The property is set to 0 to keep the default order (ABCD), or 1 to reverse the pairs (DCBA). Signed-off-by: Damien Dejean --- drivers/net/phy/realtek/Kconfig | 1 + drivers/net/phy/realtek/realtek_main.c | 64 ++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/drivers/net/phy/realtek/Kconfig b/drivers/net/phy/realtek/Kconfig index b05c2a1e9024..a741b34d193e 100644 --- a/drivers/net/phy/realtek/Kconfig +++ b/drivers/net/phy/realtek/Kconfig @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config REALTEK_PHY tristate "Realtek PHYs" + select PHY_PACKAGE help Currently supports RTL821x/RTL822x and fast ethernet PHYs diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c index 530b4e26d16e..2feb085f5c9e 100644 --- a/drivers/net/phy/realtek/realtek_main.c +++ b/drivers/net/phy/realtek/realtek_main.c @@ -171,6 +171,8 @@ #define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4) +#define RTL8224_VND1_MDI_PAIR_SWAP 0xa90 + #define RTL8366RB_POWER_SAVE 0x15 #define RTL8366RB_POWER_SAVE_ON BIT(12) @@ -1820,6 +1822,66 @@ static int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finish return rtl8224_cable_test_report(phydev, finished); } +static int rtl8224_package_modify_mmd(struct phy_device *phydev, int devad, + u32 regnum, u16 mask, u16 set) +{ + int val, ret; + + phy_lock_mdio_bus(phydev); + + val = __phy_package_read_mmd(phydev, 0, devad, regnum); + if (val < 0) { + ret = val; + goto exit; + } + + val &= ~mask; + val |= set; + + ret = __phy_package_write_mmd(phydev, 0, devad, regnum, val); + +exit: + phy_unlock_mdio_bus(phydev); + return ret; +} + +static int rtl8224_mdi_config_order(struct phy_device *phydev) +{ + struct device_node *np = phydev->mdio.dev.of_node; + u8 port_offset = phydev->mdio.addr & 3; + u32 order = 0; + int ret; + + ret = of_property_read_u32(np, "enet-phy-pair-order", &order); + + /* Do nothing in case the property is not present */ + if (ret == -EINVAL) + return 0; + + if (ret) + return ret; + + if (order & ~1) + return -EINVAL; + + return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1, + RTL8224_VND1_MDI_PAIR_SWAP, + BIT(port_offset), + order ? BIT(port_offset) : 0); +} + +static int rtl8224_config_init(struct phy_device *phydev) +{ + return rtl8224_mdi_config_order(phydev); +} + +static int rtl8224_probe(struct phy_device *phydev) +{ + /* Chip exposes 4 ports, join all of them in the same package */ + return devm_phy_package_join(&phydev->mdio.dev, phydev, + phydev->mdio.addr & ~3, 0); +} + static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) { int val; @@ -2395,6 +2457,8 @@ static struct phy_driver realtek_drvs[] = { PHY_ID_MATCH_EXACT(0x001ccad0), .name = "RTL8224 2.5Gbps PHY", .flags = PHY_POLL_CABLE_TEST, + .probe = rtl8224_probe, + .config_init = rtl8224_config_init, .get_features = rtl822x_c45_get_features, .config_aneg = rtl822x_c45_config_aneg, .read_status = rtl822x_c45_read_status, -- 2.47.3