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Mon, 16 Mar 2026 02:46:36 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Dragos Tatulea , Jianbo Liu , Leon Romanovsky Subject: [PATCH net 2/3] net/mlx5e: Prevent concurrent access to IPSec ASO context Date: Mon, 16 Mar 2026 11:46:02 +0200 Message-ID: <20260316094603.6999-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260316094603.6999-1-tariqt@nvidia.com> References: <20260316094603.6999-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06A:EE_|BN5PR12MB9512:EE_ X-MS-Office365-Filtering-Correlation-Id: 7869108c-9001-4b80-90a1-08de8340f4af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: awBM3ljdfegmskZWzjGV+aIUZx+GkeFnquzA3Unz21KFif2tNsHCpaclsXbCi2dEuT8BppoqIsuPgzKXfVYiDAJTPCGC1q+3u5NaTTtIMiMBUXnI1YIwsph74suJJKRPTYR+a828MnBt5pXQuvOF9a7Nk/eiFkJ5lluvtqpgIVh2MlzK7vzb/jjk6ElPz9ePMq32Gxr3VL7HvEGyjpgJas7MNvFMEPma9353wwGIg9uEvQOFIelECQJ1uW1bqFQWQKVk8fWIAR45QF3cmBJ229ICke/Lhff5mQ/9bB1yXl/W6rR8RrkidBLyMkN7Tx/lqJgh8/mL3/0GKN6xS5k/eFbr8WSbwfV4LeIt3KZEp6O5zAij+W6T1De2+q4bWbRZCOauCdeTFL+0EF1fJfBvsHJVB6f+hG6UKxEoJ+ZHBQk+Jnd8tY3BhErCItJUZoHlU70JB1ROSTsdk1ouZyvUDU42kkPq1qsVLEXyeV/Zi7QH/mpAqX0TxaJsWsJkQL2CabS48WB4JeAiX7fF51mD8CJOY6vVQrTrsmt/K9Dqt5CJGC95PSEPvEily13tY5AB5Qg/hiRD6nesqcGlRbKYyjRlXh4mL3/wWExEFNF0NdHAP8bS4bKiTq252mt8IyIv+atyL45ivFbNOLfJojKpjztFm2zfthSsuNSX/eGyYOM2Bz2zDevuFmLaCWNNRZi01OKFaGI+qcMqLv/xvveNsFOO57oTKpEw3z4tlDVUUxSGSQa8EIMWvGJw/jkECX36+77M5wDCjQsI3TRioG9WnA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: J7xR12jxNXbjRmX4AWEg1HFyyr2ajkAncQ6EPxzTUX50g6VS05P0WRCrKBn0fCRIxMTs6dS993Ky51la4uIkIMbVx580nLgA1aH1Uq9ClKTXawiOROoaj2QXdvX+X748hhiMWEWgHVKyUpYbATIggI1+KOLe0Q7SyPJj85dE1JRZiAMu9w5kWbmwur953BRaTm6ZrkDojR3WxsdqNE+TDhJ+Gij6Q60mxP4VkUxwU+nZRUvOzWi2HEL7FDpHxFuIqdrEl5iobeZvnsV42+Yzg+Zspa2ivyvmRorf+NouBGKBqDf3kexYEyQUwG9Eb6zsmldXNMYlK/hXmA04yPjO7fhEw8n22rhum7qwFmey3JDdCOYnZMvgsGOiku08K1qYEDd0BZUYf9YjFwtco5oL0xDQ3OFEUVtmGpim+mvFh2WElpYb3DfO0DinU5xOiv7T X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2026 09:46:53.7071 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7869108c-9001-4b80-90a1-08de8340f4af X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06A.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN5PR12MB9512 From: Jianbo Liu The query or updating IPSec offload object is through Access ASO WQE. The driver uses a single mlx5e_ipsec_aso struct for each PF, which contains a shared DMA-mapped context for all ASO operations. A race condition exists because the ASO spinlock is released before the hardware has finished processing WQE. If a second operation is initiated immediately after, it overwrites the shared context in the DMA area. When the first operation's completion is processed later, it reads this corrupted context, leading to unexpected behavior and incorrect results. This commit fixes the race by introducing a private context within each IPSec offload object. The shared ASO context is now copied to this private context while the ASO spinlock is held. Subsequent processing uses this saved, per-object context, ensuring its integrity is maintained. Fixes: 1ed78fc03307 ("net/mlx5e: Update IPsec soft and hard limits") Signed-off-by: Jianbo Liu Reviewed-by: Leon Romanovsky Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/ipsec.h | 1 + .../mellanox/mlx5/core/en_accel/ipsec_offload.c | 17 ++++++++--------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h index f8eaaf37963b..abcbd38db9db 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h @@ -287,6 +287,7 @@ struct mlx5e_ipsec_sa_entry { struct mlx5e_ipsec_dwork *dwork; struct mlx5e_ipsec_limits limits; u32 rx_mapped_id; + u8 ctx[MLX5_ST_SZ_BYTES(ipsec_aso)]; }; struct mlx5_accel_pol_xfrm_attrs { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c index 33344e00719b..71222f7247f1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c @@ -370,20 +370,18 @@ static void mlx5e_ipsec_aso_update_soft(struct mlx5e_ipsec_sa_entry *sa_entry, static void mlx5e_ipsec_handle_limits(struct mlx5e_ipsec_sa_entry *sa_entry) { struct mlx5_accel_esp_xfrm_attrs *attrs = &sa_entry->attrs; - struct mlx5e_ipsec *ipsec = sa_entry->ipsec; - struct mlx5e_ipsec_aso *aso = ipsec->aso; bool soft_arm, hard_arm; u64 hard_cnt; lockdep_assert_held(&sa_entry->x->lock); - soft_arm = !MLX5_GET(ipsec_aso, aso->ctx, soft_lft_arm); - hard_arm = !MLX5_GET(ipsec_aso, aso->ctx, hard_lft_arm); + soft_arm = !MLX5_GET(ipsec_aso, sa_entry->ctx, soft_lft_arm); + hard_arm = !MLX5_GET(ipsec_aso, sa_entry->ctx, hard_lft_arm); if (!soft_arm && !hard_arm) /* It is not lifetime event */ return; - hard_cnt = MLX5_GET(ipsec_aso, aso->ctx, remove_flow_pkt_cnt); + hard_cnt = MLX5_GET(ipsec_aso, sa_entry->ctx, remove_flow_pkt_cnt); if (!hard_cnt || hard_arm) { /* It is possible to see packet counter equal to zero without * hard limit event armed. Such situation can be if packet @@ -454,10 +452,8 @@ static void mlx5e_ipsec_handle_event(struct work_struct *_work) container_of(_work, struct mlx5e_ipsec_work, work); struct mlx5e_ipsec_sa_entry *sa_entry = work->data; struct mlx5_accel_esp_xfrm_attrs *attrs; - struct mlx5e_ipsec_aso *aso; int ret; - aso = sa_entry->ipsec->aso; attrs = &sa_entry->attrs; spin_lock_bh(&sa_entry->x->lock); @@ -466,8 +462,9 @@ static void mlx5e_ipsec_handle_event(struct work_struct *_work) goto unlock; if (attrs->replay_esn.trigger && - !MLX5_GET(ipsec_aso, aso->ctx, esn_event_arm)) { - u32 mode_param = MLX5_GET(ipsec_aso, aso->ctx, mode_parameter); + !MLX5_GET(ipsec_aso, sa_entry->ctx, esn_event_arm)) { + u32 mode_param = MLX5_GET(ipsec_aso, sa_entry->ctx, + mode_parameter); mlx5e_ipsec_update_esn_state(sa_entry, mode_param); } @@ -629,6 +626,8 @@ int mlx5e_ipsec_aso_query(struct mlx5e_ipsec_sa_entry *sa_entry, /* We are in atomic context */ udelay(10); } while (ret && time_is_after_jiffies(expires)); + if (!ret) + memcpy(sa_entry->ctx, aso->ctx, MLX5_ST_SZ_BYTES(ipsec_aso)); spin_unlock_bh(&aso->lock); return ret; } -- 2.44.0