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Mon, 16 Mar 2026 02:46:44 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Mon, 16 Mar 2026 02:46:41 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Dragos Tatulea , Jianbo Liu , Leon Romanovsky Subject: [PATCH net 3/3] net/mlx5e: Fix race condition during IPSec ESN update Date: Mon, 16 Mar 2026 11:46:03 +0200 Message-ID: <20260316094603.6999-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260316094603.6999-1-tariqt@nvidia.com> References: <20260316094603.6999-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF000000A0:EE_|BY5PR12MB4242:EE_ X-MS-Office365-Filtering-Correlation-Id: 0f189443-d8e6-4e4e-887f-08de8340f4bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|1800799024|376014|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: bJv+PZio7SrsXExXn7CfVLK2HFJu0dITvBStS3trMeWYGjEcddajgItGLj4sGSybV3oZziYGujEBXW6BTM3/hqDV2XsIR2lryosZCvd3081Ca8qXVEm2k6DZ5L5Eby4bc+l6IPcF31lFtPHaocmMoKKfS3NJNAv7bqA+F/4QZBOfNN8otm9mPOtuMD6iXt+PyglWys05xJuLfmJCbyNK4F+ME+wmXBhu22iL/qO1prlzA3U0/1bD13KWtILiFbiejauNa/bSD2ArLrp22XM+tsUyMQKMLwWUyhaF17wKuwYOdORlkXDsyRheKf9Iw9IExAqtwUOPT/wDopDDiDqcLzwl0piOQ/7x5R9iYTQEpeq3ITlN1CSLPvWw/vV5gZ/oEL/CMgx70Qz4q9+HFDGUeElxK9AgyZrfn2ltq/xvaKASwfNdqCP275eLaQa4ShkXnJJIvykNsEUytGZa8FXnyF895JFOHmvZrUFQdJh/0CtXhly9JFqci3RmlD9133mLYuiDRzIt4ZCtnUJCg/ozLtzNB3536dApLvTu7Ntu/cCYahYVZbcKu93GJ2UdnjReo41QRGAr8b3DQrIy9++XfS5qbfcpkkIbDUQMUxyicPw75vkj84QCOT04f2kaTq6Ec2ssTTENT2DinRF2lof5d4HYOs1L/6qstq4flB8FT87Nlzq12jFlEiwgJK4uEuR49hjV1bxj50fB+C98+uCxa5dGxBZSPeoH3ZP+GgRGElAjyOvH45j2EWwvfieOXwhVlXSC6u6NXkec31mqtlpeCQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(1800799024)(376014)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Mgo3750cIQCNwkdahuzCIr8LEg+8VTHABB2VDfTljqkQiqxhlMOLzk0cGgTGstfrwouCk5MsW8+T/ZS915rueeaxgUK3vCi7GE+cuvrCbvlO7OkhG9PCl4qc3yAnntB0Dxv3EOk5a1cq4DnUusyU8DkKajY3ijKJL36zjQVCRnm7OzzYE/FMQJ9yXes9d1GwuR00UZg7ld+o2GWvdNPsRjuElRfZGmmE8f6qBU9DrjNdYt47cfEZQ+1tGZsxa79sAP0O9Lw06qgCe9HDOl+rFiHKoKF4KgHgamn2oahuO+DI7cSflwl2MCpMCj56pJtQlnJeoaRYv6veaDY1RLjL77LxHzyhG6+/Vb6v8JGel1EqGS7O0oF3UAs/pNHZcaoIrMeI9D06XD1BB5xAJ0dHpVNLALEcC08ENegPYZhDH5iNbtwvOcHIv7BwLWlR8ZB4 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2026 09:46:53.8825 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f189443-d8e6-4e4e-887f-08de8340f4bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF000000A0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4242 From: Jianbo Liu In IPSec full offload mode, the device reports an ESN (Extended Sequence Number) wrap event to the driver. The driver validates this event by querying the IPSec ASO and checking that the esn_event_arm field is 0x0, which indicates an event has occurred. After handling the event, the driver must re-arm the context by setting esn_event_arm back to 0x1. A race condition exists in this handling path. After validating the event, the driver calls mlx5_accel_esp_modify_xfrm() to update the kernel's xfrm state. This function temporarily releases and re-acquires the xfrm state lock. So, need to acknowledge the event first by setting esn_event_arm to 0x1. This prevents the driver from reprocessing the same ESN update if the hardware sends events for other reason. Since the next ESN update only occurs after nearly 2^31 packets are received, there's no risk of missing an update, as it will happen long after this handling has finished. Processing the event twice causes the ESN high-order bits (esn_msb) to be incremented incorrectly. The driver then programs the hardware with this invalid ESN state, which leads to anti-replay failures and a complete halt of IPSec traffic. Fix this by re-arming the ESN event immediately after it is validated, before calling mlx5_accel_esp_modify_xfrm(). This ensures that any spurious, duplicate events are correctly ignored, closing the race window. Fixes: fef06678931f ("net/mlx5e: Fix ESN update kernel panic") Signed-off-by: Jianbo Liu Reviewed-by: Leon Romanovsky Signed-off-by: Tariq Toukan --- .../mlx5/core/en_accel/ipsec_offload.c | 33 ++++++++----------- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c index 71222f7247f1..05faad5083d9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c @@ -310,10 +310,11 @@ static void mlx5e_ipsec_aso_update(struct mlx5e_ipsec_sa_entry *sa_entry, mlx5e_ipsec_aso_query(sa_entry, data); } -static void mlx5e_ipsec_update_esn_state(struct mlx5e_ipsec_sa_entry *sa_entry, - u32 mode_param) +static void +mlx5e_ipsec_update_esn_state(struct mlx5e_ipsec_sa_entry *sa_entry, + u32 mode_param, + struct mlx5_accel_esp_xfrm_attrs *attrs) { - struct mlx5_accel_esp_xfrm_attrs attrs = {}; struct mlx5_wqe_aso_ctrl_seg data = {}; if (mode_param < MLX5E_IPSEC_ESN_SCOPE_MID) { @@ -323,18 +324,7 @@ static void mlx5e_ipsec_update_esn_state(struct mlx5e_ipsec_sa_entry *sa_entry, sa_entry->esn_state.overlap = 1; } - mlx5e_ipsec_build_accel_xfrm_attrs(sa_entry, &attrs); - - /* It is safe to execute the modify below unlocked since the only flows - * that could affect this HW object, are create, destroy and this work. - * - * Creation flow can't co-exist with this modify work, the destruction - * flow would cancel this work, and this work is a single entity that - * can't conflict with it self. - */ - spin_unlock_bh(&sa_entry->x->lock); - mlx5_accel_esp_modify_xfrm(sa_entry, &attrs); - spin_lock_bh(&sa_entry->x->lock); + mlx5e_ipsec_build_accel_xfrm_attrs(sa_entry, attrs); data.data_offset_condition_operand = MLX5_IPSEC_ASO_REMOVE_FLOW_PKT_CNT_OFFSET; @@ -451,7 +441,9 @@ static void mlx5e_ipsec_handle_event(struct work_struct *_work) struct mlx5e_ipsec_work *work = container_of(_work, struct mlx5e_ipsec_work, work); struct mlx5e_ipsec_sa_entry *sa_entry = work->data; + struct mlx5_accel_esp_xfrm_attrs tmp = {}; struct mlx5_accel_esp_xfrm_attrs *attrs; + bool need_modify = false; int ret; attrs = &sa_entry->attrs; @@ -461,19 +453,22 @@ static void mlx5e_ipsec_handle_event(struct work_struct *_work) if (ret) goto unlock; + if (attrs->lft.soft_packet_limit != XFRM_INF) + mlx5e_ipsec_handle_limits(sa_entry); + if (attrs->replay_esn.trigger && !MLX5_GET(ipsec_aso, sa_entry->ctx, esn_event_arm)) { u32 mode_param = MLX5_GET(ipsec_aso, sa_entry->ctx, mode_parameter); - mlx5e_ipsec_update_esn_state(sa_entry, mode_param); + mlx5e_ipsec_update_esn_state(sa_entry, mode_param, &tmp); + need_modify = true; } - if (attrs->lft.soft_packet_limit != XFRM_INF) - mlx5e_ipsec_handle_limits(sa_entry); - unlock: spin_unlock_bh(&sa_entry->x->lock); + if (need_modify) + mlx5_accel_esp_modify_xfrm(sa_entry, &tmp); kfree(work); } -- 2.44.0