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Mon, 16 Mar 2026 06:36:34 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Mon, 16 Mar 2026 06:36:30 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Richard Cochran" , , , , Gal Pressman , Moshe Shemesh , Dragos Tatulea , Carolina Jubran , Shahar Shitrit Subject: [PATCH net-next 1/2] net/mlx5: Move crosststamp setup into helper function Date: Mon, 16 Mar 2026 15:36:06 +0200 Message-ID: <20260316133607.8738-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260316133607.8738-1-tariqt@nvidia.com> References: <20260316133607.8738-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AF:EE_|IA0PR12MB7604:EE_ X-MS-Office365-Filtering-Correlation-Id: 672213ea-1580-4c30-3645-08de836112bc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|82310400026|36860700016|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: dje6D+XAXnL8CbHGVpkr5CwsZTfpGNIDtP/XIPxPKB+MzSd1pnvAU3R3CIQXTSOnD11A2rKSIU7XfVKtuvsPHhtV4LqMhGZEbcGy1GAXhCb1kmKGINfvOQK3q43E8dPlqmFg4UDaxGGEM5836VJ7AUVbjoVjxgiwgQFwZ+gsl21k6cvD9xQquJylz4eRtIDQ7pNiJrPC3CQRMI1aJfJgLMqvqz61pbtT75Q/cNtcdnm0ZBQJbaC7UznZOIkH1CtUOwNspg3WXnG7YERCFOSWMNBEOrD4Owuout8WC4GGcZ/fMAlAMgWMKXYIhfyVZs+90mvfN82iidnWsE2guWElc3AJA6V3b2My7fBl0hUKRxYHIA0Pu4h748pL4c4fUEWkXhURPTVb6lDBTM1ocOtf/NFZdvL6j3PMlM/p/4ppB75MsaTjXXK7reG7/l6VU0eaVmWhf6i5fktRjVly3psxqA52OdBHs9GA0ztVXQgcHwYJgNCEUhPSJZrKxLx2Ua212XvuNv7QPsC5fv9TZ/59s1wafKyC2Qa34ZBtCS5LZsyIAuOBix2B4MP5CQwuIqeWijyLGQ+QY3/OgZRrhSKJnCt8HL9DWhrqKquxq/UlH5zbG4BVSq/vGFO9VvNs4et+FnXuWyyZ+LPnbSTjUnj72N9M85XSntAEhnMxqAeijmoXGGJ/Svh9AlS8Gwitp6ONa0v2A3Y0duJ0B+omWv93M3/iUnE/PM+4qpEXUKK94U0FhpAWGzrxhONUAYJprMAWbqxM9D8p85fuXyv5Z2NYOA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(82310400026)(36860700016)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: NJKmUfLrwlH+a3efyi1h5CUE1LFJUf3ZVvt2irBzpFtJQs5ng7U2e7TsD2uIUj6H1l120A38MjzpqBk/C7dYbKv2P/e2aUwv4NA9H4jlko6+iMwDrZXRQnFrfvi5RIlaycl0H8ZlGD5jgAty1EJYeYN3SR1pbbzi1lg+sRab6mQagHzDKI256U8ywl4d2q+2/+2qd7Cm1E0fIwv6f7G4BCd+Y3iiaAck6zKVgzLHvXVGq3Cn/dk6CqWKAW1jrzht4sxXeN6AjdFWDuw+DKTR/AH+UhJNZIxJT3137TJvctg/F0siIQFgoemtwBoW0/0Dzq6H9aoutYXbBVR0fgOmKWDrJH4OBd/KYP2h6eqpv/tUdZ8kk2yUMTH3EE6IWJT6yJvMXZWvpze1A/sLJONakSVvdeIGQT1O9WasHuilPwkgkrVowO1WUhvIkGT4juzh X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2026 13:36:48.1265 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 672213ea-1580-4c30-3645-08de836112bc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7604 From: Carolina Jubran Move the crosststamp registration logic into a dedicated helper, mlx5_init_crosststamp(). This prepares the code for a follow-up patch around PTM handling. Signed-off-by: Carolina Jubran Reviewed-by: Shahar Shitrit Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 28 +++++++++++++------ 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index bd4e042077af..3322814819ea 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -1301,6 +1301,24 @@ static void mlx5_init_timer_max_freq_adjustment(struct mlx5_core_dev *mdev) min(S32_MAX, 1 << log_max_freq_adjustment); } +static void mlx5_init_crosststamp(struct mlx5_core_dev *mdev, + bool expose_cycles, struct mlx5_clock *clock) +{ +#if defined(CONFIG_X86) + if (!boot_cpu_has(X86_FEATURE_ART)) + return; + + if (!MLX5_CAP_MCAM_REG3(mdev, mtptm) || + !MLX5_CAP_MCAM_REG3(mdev, mtctr)) + return; + + clock->ptp_info.getcrosststamp = mlx5_ptp_getcrosststamp; + if (expose_cycles) + clock->ptp_info.getcrosscycles = mlx5_ptp_getcrosscycles; + +#endif /* CONFIG_X86 */ +} + static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) { struct mlx5_clock *clock = mdev->clock; @@ -1315,15 +1333,7 @@ static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) expose_cycles = !MLX5_CAP_GEN(mdev, disciplined_fr_counter) || !mlx5_real_time_mode(mdev); -#ifdef CONFIG_X86 - if (MLX5_CAP_MCAM_REG3(mdev, mtptm) && - MLX5_CAP_MCAM_REG3(mdev, mtctr) && boot_cpu_has(X86_FEATURE_ART)) { - clock->ptp_info.getcrosststamp = mlx5_ptp_getcrosststamp; - if (expose_cycles) - clock->ptp_info.getcrosscycles = - mlx5_ptp_getcrosscycles; - } -#endif /* CONFIG_X86 */ + mlx5_init_crosststamp(mdev, expose_cycles, clock); if (expose_cycles) clock->ptp_info.getcyclesx64 = mlx5_ptp_getcyclesx; -- 2.44.0