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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Richard Cochran" , , , , Gal Pressman , Moshe Shemesh , Dragos Tatulea , Carolina Jubran , Shahar Shitrit Subject: [PATCH net-next 2/2] net/mlx5: Support cross-timestamping on ARM architectures Date: Mon, 16 Mar 2026 15:36:07 +0200 Message-ID: <20260316133607.8738-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260316133607.8738-1-tariqt@nvidia.com> References: <20260316133607.8738-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B0:EE_|SA0PR12MB4494:EE_ X-MS-Office365-Filtering-Correlation-Id: acdef7aa-400e-414a-f7d6-08de83611719 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|1800799024|376014|7416014|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: a2mUfQEAfgEFr4uK3v23A4ARhgz1F6mMVHMjzQcgOqYQzfHcwyyLvx7/pVcxwpZT6DjJ0gidnU4b33XFxevOEPg/7Z6+gccE34bHSg3eZK5WEHzXkpgvt8+p3QV8bzxRzTcE4wDc5otQzC3jNhvgZ4YwyoNk3Z4vbUTUZyN/ceORbwp4Y7BOujsZBYXI9dzxTsZH5ZvjcVoVFo+shaTNBtz8YCsMhXWgBukm74OQFgALu2TTxDmzWjLDJfRS/hMBvTz5F76mCxspHeIJqIMwt+QB7+pMbXtOSraeeJ5mMKY4iy4sik63UPeiG9cQiFC+efoHfnbXtiPdbg/1cvE82PIIiHgMIyHkNwSPkw4P5LWZ8NaSm/vrY50C7XewZXuj6mlhvsWjiNB9YcrMRxyaub3aAESyIpva57uNWeQLNVV0G/M9sUIvkLoqgH1mVqlRNiUoOucMVZhchoSvv10gpeDJ9A5/A8X3Moz1BOKF13phA2Wa9uuPhTT3PmIpiU5QNHfZpaKHY7vGqIARKiUASmmORz5oXTEDYsc/8a1hS+yh6Fl42XTf1kUhpcuuqfa1aCd/u7CyTFzSeDkMcuqgvY1nkaGO1LLVTnPA2/cTa+xVgf457//MMO1ommCBYu/xHo+RLPVZP6A3mimASkUthebt/zslCTqsPI8PS1xc66Kf8RPLHluBtBCwRskI4zgEaRCMMguUNtI/mnDv9LI2UtedJppMH/yJBwIVmdHR0LbZLritBHJ+c1srJOGRGzo5RjT4Tbt5j2wiQtPftInTJA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(1800799024)(376014)(7416014)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5ktpcTuczmsO6ghdSPEPFvfdnpWcKO9J02szR2dv1+jRKj3elUbLTMjwZ6ehHBLedMcxnG8F6fDmE98kQo5R/WDMQMkrEWEfXRp2qfqrVQmHeKVAIT1fvt3SuUBB/3GDVcu0o+amMG/M3lbvRxc2clpiu5VzXEjCpEEmGL5nEfBJCMcR/X6rZrXNEs9SnANqfS2hDhz3g05wVOqy/b9J5t3Ro6iM0lIgP3WUqYa+keO15oQnpDzAIUKYRpDZXANN+t0rfVn09yjTkHsRon71Ph+ccZKgl8EmUySVneY5PB2E6ByslsdthSP5oiu0wkD/sSuK+sBHh06KXq2peNtu9mW4s/lr+Xofzeu7KYvbTRXS1DDQbHtzonB6qS2MAJm3erEvk1/byXrLp8sSRbIeZOvMZQDZkgdif/td1qjlEuvnH01WWv8AXOErD5V/CSXf X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2026 13:36:55.4389 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: acdef7aa-400e-414a-f7d6-08de83611719 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4494 From: Carolina Jubran Extend cross-timestamp support for ARM systems that implement the ARM architected timer. Signed-off-by: Carolina Jubran Reviewed-by: Shahar Shitrit Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/lib/clock.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index 3322814819ea..d785f1b4f2e1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -38,10 +38,10 @@ #include "lib/eq.h" #include "en.h" #include "clock.h" -#ifdef CONFIG_X86 +#if defined(CONFIG_X86) || defined(CONFIG_ARM_ARCH_TIMER) #include #include -#endif /* CONFIG_X86 */ +#endif /* CONFIG_X86 || CONFIG_ARM_ARCH_TIMER */ #define MLX5_RT_CLOCK_IDENTITY_SIZE MLX5_FLD_SZ_BYTES(mrtcq_reg, rt_clock_identity) @@ -229,7 +229,7 @@ static int mlx5_set_mtutc(struct mlx5_core_dev *dev, u32 *mtutc, u32 size) MLX5_REG_MTUTC, 0, 1); } -#ifdef CONFIG_X86 +#if defined(CONFIG_X86) || defined(CONFIG_ARM_ARCH_TIMER) static bool mlx5_is_ptm_source_time_available(struct mlx5_core_dev *dev) { u32 out[MLX5_ST_SZ_DW(mtptm_reg)] = {0}; @@ -275,7 +275,8 @@ static int mlx5_mtctr_read(struct mlx5_core_dev *mdev, host = MLX5_GET64(mtctr_reg, out, first_clock_timestamp); *sys_counterval = (struct system_counterval_t) { .cycles = host, - .cs_id = CSID_X86_ART, + .cs_id = IS_ENABLED(CONFIG_X86) ? CSID_X86_ART : + CSID_ARM_ARCH_COUNTER, .use_nsecs = true, }; *device = MLX5_GET64(mtctr_reg, out, second_clock_timestamp); @@ -373,7 +374,7 @@ static int mlx5_ptp_getcrosscycles(struct ptp_clock_info *ptp, mlx5_clock_unlock(clock); return err; } -#endif /* CONFIG_X86 */ +#endif /* CONFIG_X86 || CONFIG_ARM_ARCH_TIMER */ static u64 mlx5_read_time(struct mlx5_core_dev *dev, struct ptp_system_timestamp *sts, @@ -1307,7 +1308,8 @@ static void mlx5_init_crosststamp(struct mlx5_core_dev *mdev, #if defined(CONFIG_X86) if (!boot_cpu_has(X86_FEATURE_ART)) return; - +#endif /* CONFIG_X86 */ +#if defined(CONFIG_X86) || defined(CONFIG_ARM_ARCH_TIMER) if (!MLX5_CAP_MCAM_REG3(mdev, mtptm) || !MLX5_CAP_MCAM_REG3(mdev, mtctr)) return; @@ -1316,7 +1318,7 @@ static void mlx5_init_crosststamp(struct mlx5_core_dev *mdev, if (expose_cycles) clock->ptp_info.getcrosscycles = mlx5_ptp_getcrosscycles; -#endif /* CONFIG_X86 */ +#endif /* CONFIG_X86 || CONFIG_ARM_ARCH_TIMER */ } static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) -- 2.44.0