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Thu, 19 Mar 2026 00:44:08 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Dragos Tatulea Subject: [PATCH net-next 2/3] net/mlx5e: RX, Pre-calculate pad value in MPWQE Date: Thu, 19 Mar 2026 09:43:37 +0200 Message-ID: <20260319074338.24265-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260319074338.24265-1-tariqt@nvidia.com> References: <20260319074338.24265-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3D:EE_|BY5PR12MB4209:EE_ X-MS-Office365-Filtering-Correlation-Id: 22b3746a-f5a0-4731-bbae-08de858b59b8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|1800799024|82310400026|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: g/N6Cf/8zPfEFZv3xyZw/8QU1Cx1JU3XU2fz7/CmzPuW/wV/EJqMY4vQUc7+2qb2jloRfi5ESaP8Ms0aP9QDkXvHv9czU9PRNjwNPY7GddA1Z24ZNXr/RNJ1OMDSZd0CaaavSlKsvoBPZ+JVmAGSbcJx9aQKm/I4yaEMSadisZcw38tUnzN7ZGNMQQlJ7LbAVMvixuVuYlIJzOVuzQ8AS2ZfHT+TfRMHSZ2w8RVgdukyd6Oy4QP1+mALO2UlCb1nW+RBgZtFizpyobFzd1EjqsLV5b6bAt/kCIa5RMCOxkaf6pCfft0yut8jvdKCBaB+GSA9AP0PH8on9c/hMDWqZHv5krnXTIhMfGnt6pG8UOjs/2rnmKAC9s7cXY9BnvjXdkDti5RbW/er4GcXUhD9mRZqZFq+Ph6mKZC8sqDMGGBoBwuwm8RETtASxMCL0jIySuMHnP+Y/XrkxzRRlpTPHy7iWt5HjCYFk2asLtrYAiUZrTni3Co/sr7Mhi8fiVTBSXy0Y1owEwTge2TnDOf3cR9l0SGEOPss+rDpJBfH5gNsuwdNvXQS+mvaf3wOPwEKzflP2WXT2dDdmB7ReBNfq5h6K46odaIFCCzt3Fs20WW5IXxoMjgGtSVUDattTdI0kCW3P8CTd7X29focY69Yj7+rRpEty9id00/h2wIF/BS51z4bPZJTyKDKII21d6tFWbvY7O7GYrbW9vnEAzOSvgxalR6Tu8p/4bWnG/M+sVLEGnPxST/lZ/sM5WxswLEqQqf/sQONIeFIRE0EAXJK5g== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700016)(1800799024)(82310400026)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4FgSBdi7X9B8nweefzLpdEuLBf84SOt/G6PXyM9D1t+aBnJzS06QT2+k6ieK5hCdY+O9b+BP1fIyg9zdEFw7HPFyorHsk2Re25MIGdvghPeTigj5cz2KNd6RvsXEBndhqpedqJrcJFn6dh7i6X7cAyO7gXk0Z1nofDzGEyLTcLrbpjYW2b1AOLnDQJMHMWPT4BoSKutoShOvdnrcuoAM+lvUBFvk0Ce8AnNuoj/pkh8Ikz76l5wXlTd6CRodEEJh3s1ntGWG09evofodqbq1ynVFo6/5YEiYyYxS9Km2EqiQK5E/Ps8Ltz7tzXJvlP9l+KdPelCjzl9HsaCKi1FXmsAGJxyw6/eTbOOJTB2nlD6sBixn5ab2kSI0JTwxBMW5rl6wgkk/ppPMkA/nMREgc4zri7ens97Kx7kRiM85pClIDCCOa+RCd8R/Zv4lIAI2 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2026 07:44:28.4070 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22b3746a-f5a0-4731-bbae-08de858b59b8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4209 Introduce a dedicated function that calculates the needed entries padding in a UMR WQE. Use it to pre-calculate the padding value and save it on the RQ struct. Signed-off-by: Tariq Toukan Reviewed-by: Dragos Tatulea --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 14 ++++++++++++++ drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 8 ++------ 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index d90be82a9019..6c773a75b514 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -685,6 +685,7 @@ struct mlx5e_rq { u8 min_wqe_bulk; u8 page_shift; u8 pages_per_wqe; + u8 entries_pad; u8 umr_wqebbs; u8 mtts_per_wqe; u8 umr_mode; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 20c24d829ee2..5a31c79cec06 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -307,6 +307,17 @@ static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv) mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb); } +static u8 mlx5e_mpwrq_umr_entries_pad(u32 entries, + enum mlx5e_mpwrq_umr_mode umr_mode) +{ + u8 umr_entry_size = mlx5e_mpwrq_umr_entry_size(umr_mode); + u32 sz; + + sz = entries * umr_entry_size; + + return ALIGN(sz, MLX5_UMR_FLEX_ALIGNMENT) - sz; +} + static u16 mlx5e_mpwrq_umr_octowords(u32 entries, enum mlx5e_mpwrq_umr_mode umr_mode) { u8 umr_entry_size = mlx5e_mpwrq_umr_entry_size(umr_mode); @@ -904,6 +915,9 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, rq->mpwqe.pages_per_wqe = mlx5e_mpwrq_pages_per_wqe(mdev, rq->mpwqe.page_shift, rq->mpwqe.umr_mode); + rq->mpwqe.entries_pad = + mlx5e_mpwrq_umr_entries_pad(rq->mpwqe.pages_per_wqe, + rq->mpwqe.umr_mode); rq->mpwqe.umr_wqebbs = mlx5e_mpwrq_umr_wqebbs(mdev, rq->mpwqe.page_shift, rq->mpwqe.umr_mode); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c index f5c0e2a0ada9..580bb51ad7ef 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -645,13 +645,9 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) /* Pad if needed, in case the value set to ucseg->xlt_octowords * in mlx5e_build_umr_wqe() needed alignment. */ - if (rq->mpwqe.pages_per_wqe & (MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT - 1)) { - int pad = ALIGN(rq->mpwqe.pages_per_wqe, MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT) - - rq->mpwqe.pages_per_wqe; - + if (rq->mpwqe.entries_pad) memset(&umr_wqe->inline_mtts[rq->mpwqe.pages_per_wqe], 0, - sizeof(*umr_wqe->inline_mtts) * pad); - } + rq->mpwqe.entries_pad); bitmap_zero(wi->skip_release_bitmap, rq->mpwqe.pages_per_wqe); wi->consumed_strides = 0; -- 2.44.0