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From: Simon Horman <horms@kernel.org>
To: Grzegorz Nitka <grzegorz.nitka@intel.com>
Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
	intel-wired-lan@lists.osuosl.org, poros@redhat.com,
	richardcochran@gmail.com, andrew+netdev@lunn.ch,
	przemyslaw.kitszel@intel.com, anthony.l.nguyen@intel.com,
	Prathosh.Satish@microchip.com, ivecera@redhat.com,
	jiri@resnulli.us, arkadiusz.kubalewski@intel.com,
	vadim.fedorenko@linux.dev, donald.hunter@gmail.com,
	pabeni@redhat.com, kuba@kernel.org, davem@davemloft.net,
	Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Subject: Re: [PATCH net-next 1/8] dpll: add new DPLL type for transmit clock (TXC) usage
Date: Thu, 19 Mar 2026 17:45:03 +0000	[thread overview]
Message-ID: <20260319174503.GO1753385@horms.kernel.org> (raw)
In-Reply-To: <20260318090654.611349-2-grzegorz.nitka@intel.com>

On Wed, Mar 18, 2026 at 10:06:47AM +0100, Grzegorz Nitka wrote:
> Extend the DPLL subsystem with a new DPLL type, DPLL_TYPE_TXC,
> representing devices that drive a transmit reference clock. Certain
> PHYs, MACs and SerDes blocks use a dedicated TX reference clock for
> link operation, and this clock domain is distinct from PPS- and
> EEC-driven synchronization sources. Defining a dedicated type allows
> user space and drivers to correctly classify and configure DPLLs
> intended for TX clock generation.
> 
> The corresponding netlink specification is updated to expose "txc"
> 
> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
> ---
>  Documentation/netlink/specs/dpll.yaml | 3 +++
>  include/uapi/linux/dpll.h             | 2 ++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/specs/dpll.yaml
> index 3dd48a32f783..2a2ee37a1fc0 100644
> --- a/Documentation/netlink/specs/dpll.yaml
> +++ b/Documentation/netlink/specs/dpll.yaml
> @@ -138,6 +138,9 @@ definitions:
>        -
>          name: eec
>          doc: dpll drives the Ethernet Equipment Clock
> +      -
> +        name: txc
> +        doc: dpll drives Tx reference clock
>      render-max: true
>    -
>      type: enum
> diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h
> index de0005f28e5c..a277d08ac264 100644
> --- a/include/uapi/linux/dpll.h
> +++ b/include/uapi/linux/dpll.h
> @@ -109,10 +109,12 @@ enum dpll_clock_quality_level {
>   * enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute
>   * @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal
>   * @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock
> + * @DPLL_TYPE_TXC: dpll drives Tx reference clock signal
>   */
>  enum dpll_type {
>  	DPLL_TYPE_PPS = 1,
>  	DPLL_TYPE_EEC,
> +	DPLL_TYPE_TXC,
>  
>  	/* private: */
>  	__DPLL_TYPE_MAX,

I think that the spec and source code changes are inconsistent in this
patch.

With it applied I see:

./tools/net/ynl/ynl-regen.sh -f && git diff
diff --git a/drivers/dpll/dpll_nl.c b/drivers/dpll/dpll_nl.c
index a2b22d492114..4182bdbb6dbb 100644
--- a/drivers/dpll/dpll_nl.c
+++ b/drivers/dpll/dpll_nl.c
@@ -34,7 +34,7 @@ const struct nla_policy dpll_reference_sync_nl_policy[DPLL_A_PIN_STATE + 1] = {
 static const struct nla_policy dpll_device_id_get_nl_policy[DPLL_A_TYPE + 1] = {
        [DPLL_A_MODULE_NAME] = { .type = NLA_NUL_STRING, },
        [DPLL_A_CLOCK_ID] = { .type = NLA_U64, },
-       [DPLL_A_TYPE] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
+       [DPLL_A_TYPE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
 };

 /* DPLL_CMD_DEVICE_GET - do */
diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h
index a277d08ac264..8f6db5d5bf0c 100644
--- a/include/uapi/linux/dpll.h
+++ b/include/uapi/linux/dpll.h
@@ -109,7 +109,7 @@ enum dpll_clock_quality_level {
  * enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute
  * @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal
  * @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock
- * @DPLL_TYPE_TXC: dpll drives Tx reference clock signal
+ * @DPLL_TYPE_TXC: dpll drives Tx reference clock
  */
 enum dpll_type {
        DPLL_TYPE_PPS = 1,

-- 
pw-bot: changes-requested

  reply	other threads:[~2026-03-19 17:45 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-18  9:06 [PATCH net-next 0/8] dpll/ice: Add TXC DPLL type and full TX reference clock control for E825 Grzegorz Nitka
2026-03-18  9:06 ` [PATCH net-next 1/8] dpll: add new DPLL type for transmit clock (TXC) usage Grzegorz Nitka
2026-03-19 17:45   ` Simon Horman [this message]
2026-03-19 18:07     ` Nitka, Grzegorz
2026-03-18  9:06 ` [PATCH net-next 2/8] dpll: allow registering FW-identified pin with a different DPLL Grzegorz Nitka
2026-03-18  9:06 ` [PATCH net-next 3/8] dpll: extend pin notifier and netlink events with notification source ID Grzegorz Nitka
2026-03-18  9:06 ` [PATCH net-next 4/8] dpll: zl3073x: allow SyncE_Ref pin state change Grzegorz Nitka
2026-03-18  9:06 ` [PATCH net-next 5/8] ice: add TX clock (TXC) DPLL interface for E825 devices Grzegorz Nitka
2026-03-19 17:37   ` Simon Horman
2026-03-21 20:33     ` Nitka, Grzegorz
2026-03-18  9:06 ` [PATCH net-next 6/8] ice: implement CPI support for E825C Grzegorz Nitka
2026-03-18  9:06 ` [PATCH net-next 7/8] ice: add Tx reference clock index handling to AN restart command Grzegorz Nitka
2026-03-18 10:02   ` [Intel-wired-lan] " Loktionov, Aleksandr
2026-03-18  9:06 ` [PATCH net-next 8/8] ice: add TX reference clock (tx_clk) control for E825 devices Grzegorz Nitka

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