From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [52.237.72.81]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 16F292E7631; Tue, 24 Mar 2026 07:34:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=52.237.72.81 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774337666; cv=none; b=ZSXwyRL3sZ/yoZH0+bBstSJ3DzL2JnEsXUR5Ac5fvAusQQiz5G0vj4im0pZzQz2/qS3/hZtbHDHdOADZu4qnrMqmUc19l7ZxNmNrghjS68qB+tgOmqv10nmmmtA6AXA5bVLUzvoI2B46iCqQPBKAslALf2/yHF99Qpcx3kfBPbM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774337666; c=relaxed/simple; bh=z4n3PCrtTDdq36Yvi4h1mo7cmkQTPxqEfzbacDx+P6Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cL246dJrkKcExkGFy8FokWtUadH0Bgjs6fQegTLUd6fx5XhvNSuYiq3ANpaJ2PXTkllTh3k0i1ntX+Jo2Y48zU/SDkKi1T8K+i4EDEJXfisyMDaaV35YIuhbyW0SLFJs4DlFbXKmq0YxyuOgxG+C4RRAxwpdM8EvXFLe7AZ+XgA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=52.237.72.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0004057DT.eswin.cn (unknown [10.11.96.26]) by app1 (Coremail) with SMTP id TAJkCgAXrHBgPsJpwDsLAA--.21779S2; Tue, 24 Mar 2026 15:33:53 +0800 (CST) From: lizhi2@eswincomputing.com To: devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maxime.chevallier@bootlin.com Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com, horms@kernel.org, Zhi Li Subject: [PATCH net-next v5 2/3] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing Date: Tue, 24 Mar 2026 15:32:05 +0800 Message-ID: <20260324073350.419-1-lizhi2@eswincomputing.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260324073017.376-1-lizhi2@eswincomputing.com> References: <20260324073017.376-1-lizhi2@eswincomputing.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CM-TRANSID:TAJkCgAXrHBgPsJpwDsLAA--.21779S2 X-Coremail-Antispam: 1UD129KBjvJXoW3Zw4ktF15AF1xAFyUtrWDArb_yoWDWFy5pF WkAFy5tr1jqr1fG3yvyF4kta4Fkw47WF1rArWfKFnFyF98trn8XayjyasIkF98Wry7Zr13 J3yUAFyxuF129rJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r4a6rW5MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1U MIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTRMrWrDUUUU X-CM-SenderInfo: xol2xx2s6h245lqf0zpsxwx03jof0z/ From: Zhi Li The second Ethernet controller (eth1) on the Eswin EIC7700 SoC may fail to sample RX data correctly at Gigabit speed due to EIC7700-specific receive clock to data skew at the MAC input in the silicon. The existing internal delay configuration does not provide sufficient adjustment range to compensate for this condition at 1000Mbps. Update the EIC7700 DWMAC glue driver to apply EIC7700-specific clock sampling inversion only during Gigabit operation on MAC instances that require it. TXD and RXD delay registers are explicitly cleared during initialization to override any residual configuration left by the bootloader. All HSP CSR register accesses are performed only after the required clocks are enabled. Fixes: ea77dbbdbc4e ("net: stmmac: add Eswin EIC7700 glue driver") Signed-off-by: Zhi Li --- .../ethernet/stmicro/stmmac/dwmac-eic7700.c | 183 ++++++++++++++---- 1 file changed, 140 insertions(+), 43 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c index bcb8e000e720..33144611da8d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c @@ -28,20 +28,40 @@ /* * TX/RX Clock Delay Bit Masks: - * - TX Delay: bits [14:8] — TX_CLK delay (unit: 0.1ns per bit) - * - RX Delay: bits [30:24] — RX_CLK delay (unit: 0.1ns per bit) + * - TX Delay: bits [14:8] — TX_CLK delay (unit: 0.02ns per bit) + * - TX Invert : bit [15] + * - RX Delay: bits [30:24] — RX_CLK delay (unit: 0.02ns per bit) + * - RX Invert : bit [31] */ #define EIC7700_ETH_TX_ADJ_DELAY GENMASK(14, 8) #define EIC7700_ETH_RX_ADJ_DELAY GENMASK(30, 24) +#define EIC7700_ETH_TX_INV_DELAY BIT(15) +#define EIC7700_ETH_RX_INV_DELAY BIT(31) -#define EIC7700_MAX_DELAY_UNIT 0x7F +#define EIC7700_MAX_DELAY_STEPS 0x7F +#define EIC7700_DELAY_STEP_PS 20 +#define EIC7700_MAX_DELAY_PS \ + (EIC7700_MAX_DELAY_STEPS * EIC7700_DELAY_STEP_PS) static const char * const eic7700_clk_names[] = { "tx", "axi", "cfg", }; +struct eic7700_dwmac_data { + bool rgmii_rx_clk_invert; +}; + struct eic7700_qos_priv { + struct device *dev; struct plat_stmmacenet_data *plat_dat; + struct regmap *eic7700_hsp_regmap; + u32 eth_axi_lp_ctrl_offset; + u32 eth_phy_ctrl_offset; + u32 eth_txd_offset; + u32 eth_clk_offset; + u32 eth_rxd_offset; + u32 eth_clk_dly_param; + bool eth_rx_clk_inv; }; static int eic7700_clks_config(void *priv, bool enabled) @@ -61,8 +81,28 @@ static int eic7700_clks_config(void *priv, bool enabled) static int eic7700_dwmac_init(struct device *dev, void *priv) { struct eic7700_qos_priv *dwc = priv; + int ret; + + ret = eic7700_clks_config(dwc, true); + if (ret) + return ret; + + ret = regmap_set_bits(dwc->eic7700_hsp_regmap, + dwc->eth_phy_ctrl_offset, + EIC7700_ETH_TX_CLK_SEL | + EIC7700_ETH_PHY_INTF_SELI); + if (ret) { + eic7700_clks_config(dwc, false); + return ret; + } + + regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_axi_lp_ctrl_offset, + EIC7700_ETH_CSYSREQ_VAL); + + regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_txd_offset, 0); + regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_rxd_offset, 0); - return eic7700_clks_config(dwc, true); + return 0; } static void eic7700_dwmac_exit(struct device *dev, void *priv) @@ -88,18 +128,35 @@ static int eic7700_dwmac_resume(struct device *dev, void *priv) return ret; } +static void eic7700_dwmac_fix_speed(void *priv, phy_interface_t interface, + int speed, unsigned int mode) +{ + struct eic7700_qos_priv *dwc = (struct eic7700_qos_priv *)priv; + u32 dly_param = dwc->eth_clk_dly_param; + + switch (speed) { + case SPEED_1000: + if (dwc->eth_rx_clk_inv) + dly_param |= EIC7700_ETH_RX_INV_DELAY; + break; + case SPEED_100: + case SPEED_10: + break; + default: + dev_err(dwc->dev, "invalid speed %u\n", speed); + break; + } + + regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_clk_offset, dly_param); +} + static int eic7700_dwmac_probe(struct platform_device *pdev) { + const struct eic7700_dwmac_data *data; struct plat_stmmacenet_data *plat_dat; struct stmmac_resources stmmac_res; struct eic7700_qos_priv *dwc_priv; - struct regmap *eic7700_hsp_regmap; - u32 eth_axi_lp_ctrl_offset; - u32 eth_phy_ctrl_offset; - u32 eth_phy_ctrl_regset; - u32 eth_rxd_dly_offset; - u32 eth_dly_param = 0; - u32 delay_ps; + u32 delay_ps, val; int i, ret; ret = stmmac_get_platform_resources(pdev, &stmmac_res); @@ -116,70 +173,95 @@ static int eic7700_dwmac_probe(struct platform_device *pdev) if (!dwc_priv) return -ENOMEM; + dwc_priv->dev = &pdev->dev; + + data = device_get_match_data(&pdev->dev); + if (!data) + return dev_err_probe(&pdev->dev, + -EINVAL, "no match data found\n"); + + dwc_priv->eth_rx_clk_inv = data->rgmii_rx_clk_invert; + /* Read rx-internal-delay-ps and update rx_clk delay */ if (!of_property_read_u32(pdev->dev.of_node, "rx-internal-delay-ps", &delay_ps)) { - u32 val = min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT); + if (delay_ps % EIC7700_DELAY_STEP_PS) + return dev_err_probe(&pdev->dev, -EINVAL, + "rx delay must be multiple of %dps\n", + EIC7700_DELAY_STEP_PS); + + if (delay_ps > EIC7700_MAX_DELAY_PS) + return dev_err_probe(&pdev->dev, -EINVAL, + "rx delay out of range\n"); - eth_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY; - eth_dly_param |= FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val); - } else { - return dev_err_probe(&pdev->dev, -EINVAL, - "missing required property rx-internal-delay-ps\n"); + val = delay_ps / EIC7700_DELAY_STEP_PS; + + dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY; + dwc_priv->eth_clk_dly_param |= + FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val); } /* Read tx-internal-delay-ps and update tx_clk delay */ if (!of_property_read_u32(pdev->dev.of_node, "tx-internal-delay-ps", &delay_ps)) { - u32 val = min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT); + if (delay_ps % EIC7700_DELAY_STEP_PS) + return dev_err_probe(&pdev->dev, -EINVAL, + "tx delay must be multiple of %dps\n", + EIC7700_DELAY_STEP_PS); + + if (delay_ps > EIC7700_MAX_DELAY_PS) + return dev_err_probe(&pdev->dev, -EINVAL, + "tx delay out of range\n"); + + val = delay_ps / EIC7700_DELAY_STEP_PS; - eth_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY; - eth_dly_param |= FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val); - } else { - return dev_err_probe(&pdev->dev, -EINVAL, - "missing required property tx-internal-delay-ps\n"); + dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY; + dwc_priv->eth_clk_dly_param |= + FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val); } - eic7700_hsp_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "eswin,hsp-sp-csr"); - if (IS_ERR(eic7700_hsp_regmap)) + dwc_priv->eic7700_hsp_regmap = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "eswin,hsp-sp-csr"); + if (IS_ERR(dwc_priv->eic7700_hsp_regmap)) return dev_err_probe(&pdev->dev, - PTR_ERR(eic7700_hsp_regmap), + PTR_ERR(dwc_priv->eic7700_hsp_regmap), "Failed to get hsp-sp-csr regmap\n"); ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,hsp-sp-csr", - 1, ð_phy_ctrl_offset); + 1, &dwc_priv->eth_phy_ctrl_offset); if (ret) return dev_err_probe(&pdev->dev, ret, "can't get eth_phy_ctrl_offset\n"); - regmap_read(eic7700_hsp_regmap, eth_phy_ctrl_offset, - ð_phy_ctrl_regset); - eth_phy_ctrl_regset |= - (EIC7700_ETH_TX_CLK_SEL | EIC7700_ETH_PHY_INTF_SELI); - regmap_write(eic7700_hsp_regmap, eth_phy_ctrl_offset, - eth_phy_ctrl_regset); - ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,hsp-sp-csr", - 2, ð_axi_lp_ctrl_offset); + 2, &dwc_priv->eth_axi_lp_ctrl_offset); if (ret) return dev_err_probe(&pdev->dev, ret, "can't get eth_axi_lp_ctrl_offset\n"); - regmap_write(eic7700_hsp_regmap, eth_axi_lp_ctrl_offset, - EIC7700_ETH_CSYSREQ_VAL); + ret = of_property_read_u32_index(pdev->dev.of_node, + "eswin,hsp-sp-csr", + 3, &dwc_priv->eth_clk_offset); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "can't get eth_clk_offset\n"); ret = of_property_read_u32_index(pdev->dev.of_node, "eswin,hsp-sp-csr", - 3, ð_rxd_dly_offset); + 4, &dwc_priv->eth_txd_offset); if (ret) return dev_err_probe(&pdev->dev, ret, - "can't get eth_rxd_dly_offset\n"); + "can't get eth_txd_offset\n"); - regmap_write(eic7700_hsp_regmap, eth_rxd_dly_offset, - eth_dly_param); + ret = of_property_read_u32_index(pdev->dev.of_node, + "eswin,hsp-sp-csr", + 5, &dwc_priv->eth_rxd_offset); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "can't get eth_rxd_offset\n"); plat_dat->num_clks = ARRAY_SIZE(eic7700_clk_names); plat_dat->clks = devm_kcalloc(&pdev->dev, @@ -208,12 +290,27 @@ static int eic7700_dwmac_probe(struct platform_device *pdev) plat_dat->exit = eic7700_dwmac_exit; plat_dat->suspend = eic7700_dwmac_suspend; plat_dat->resume = eic7700_dwmac_resume; + plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed; return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); } +static const struct eic7700_dwmac_data eic7700_dwmac_data = { + .rgmii_rx_clk_invert = false, +}; + +static const struct eic7700_dwmac_data eic7700_dwmac_data_clk_inversion = { + .rgmii_rx_clk_invert = true, +}; + static const struct of_device_id eic7700_dwmac_match[] = { - { .compatible = "eswin,eic7700-qos-eth" }, + { .compatible = "eswin,eic7700-qos-eth", + .data = &eic7700_dwmac_data, + }, + { + .compatible = "eswin,eic7700-qos-eth-clk-inversion", + .data = &eic7700_dwmac_data_clk_inversion, + }, { } }; MODULE_DEVICE_TABLE(of, eic7700_dwmac_match); -- 2.25.1