From: Suraj Gupta <suraj.gupta2@amd.com>
To: <andrew+netdev@lunn.ch>, <davem@davemloft.net>,
<edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>,
<michal.simek@amd.com>, <sean.anderson@linux.dev>,
<radhey.shyam.pandey@amd.com>, <horms@kernel.org>
Cc: <netdev@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <harini.katakam@amd.com>
Subject: [PATCH net 1/2] net: xilinx: axienet: Correct BD length masks to match AXIDMA IP spec
Date: Tue, 24 Mar 2026 20:23:51 +0530 [thread overview]
Message-ID: <20260324145353.1899248-2-suraj.gupta2@amd.com> (raw)
In-Reply-To: <20260324145353.1899248-1-suraj.gupta2@amd.com>
The XAXIDMA_BD_CTRL_LENGTH_MASK and XAXIDMA_BD_STS_ACTUAL_LEN_MASK
macros were defined as 0x007FFFFF (23 bits), but the AXI DMA IP
product guide (PG021) specifies the buffer length field as bits 25:0
(26 bits). Update both masks to 0x03FFFFFF to match the IP
documentation.
In practice this had no functional impact, since Ethernet frames are
far smaller than 2^23 bytes and the extra bits were always zero, but
the masks should still reflect the hardware specification.
Fixes: 8a3b7a252dca ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
---
drivers/net/ethernet/xilinx/xilinx_axienet.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
index 5ff742103beb..602389843342 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
@@ -105,7 +105,7 @@
#define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /* Whether has DRE mask */
#define XAXIDMA_BD_WORDLEN_MASK 0xFF /* Whether has DRE mask */
-#define XAXIDMA_BD_CTRL_LENGTH_MASK 0x007FFFFF /* Requested len */
+#define XAXIDMA_BD_CTRL_LENGTH_MASK 0x03FFFFFF /* Requested len */
#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
#define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
@@ -130,7 +130,7 @@
#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
#define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
-#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
+#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x03FFFFFF /* Actual len */
#define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /* Completed */
#define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /* Decode error */
#define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /* Slave error */
--
2.49.1
next prev parent reply other threads:[~2026-03-24 14:54 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-24 14:53 [PATCH net 0/2] Correct BD length masks and BQL accounting for multi-BD TX packets Suraj Gupta
2026-03-24 14:53 ` Suraj Gupta [this message]
2026-03-24 16:09 ` [PATCH net 1/2] net: xilinx: axienet: Correct BD length masks to match AXIDMA IP spec Sean Anderson
2026-03-24 14:53 ` [PATCH net 2/2] net: xilinx: axienet: Fix BQL accounting for multi-BD TX packets Suraj Gupta
2026-03-24 16:09 ` Sean Anderson
2026-03-25 5:30 ` Gupta, Suraj
2026-03-26 15:38 ` Sean Anderson
2026-03-26 19:51 ` Gupta, Suraj
2026-03-26 19:56 ` Sean Anderson
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