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Thu, 26 Mar 2026 00:00:38 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Thu, 26 Mar 2026 00:00:35 -0700 Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Thu, 26 Mar 2026 00:00:35 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Thu, 26 Mar 2026 00:00:35 -0700 Received: from kernel-ep2 (unknown [10.29.36.53]) by maili.marvell.com (Postfix) with SMTP id BE49A3F7077; Thu, 26 Mar 2026 00:00:31 -0700 (PDT) Date: Thu, 26 Mar 2026 12:30:30 +0530 From: Subbaraya Sundeep To: Simon Horman CC: , , , , , , , , , Subject: Re: [net-next PATCH v2 4/4] octeontx2-pf: cn20k: Use unified Halo context Message-ID: <20260326070030.GA1276961@kernel-ep2> References: <1773920826-16985-5-git-send-email-sbhatta@marvell.com> <20260320165037.96305-1-horms@kernel.org> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260320165037.96305-1-horms@kernel.org> X-Authority-Analysis: v=2.4 cv=b4q/I9Gx c=1 sm=1 tr=0 ts=69c4d996 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=kj9zAlcOel0A:10 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=qit2iCtTFQkLgVSMPQTB:22 a=9R54UkLUAAAA:8 a=VwQbUJbxAAAA:8 a=hM8Av25v_7ZSUbZF0EwA:9 a=CjuIK1q_8ugA:10 a=YTcpBFlVQWkNscrzJ_Dz:22 X-Proofpoint-ORIG-GUID: cfYzsdCj9b_rbahtQRhw92nV947suUmK X-Proofpoint-GUID: cfYzsdCj9b_rbahtQRhw92nV947suUmK X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI2MDA1MSBTYWx0ZWRfX7CfhkEw1gY2I Y5+f17Y7e14WRE5tgNPkacajP4ylMVo7+U/8P8UtDTtk8fGAXfWCxtveKmMd42DQ8KQKUKzigya TRX7rVRW03cE1gayQgledQgOViYj5qRnstlc6IaoTqttdQ/41kiiRIsW2gF5uQu4dLXF0DwaOj3 TemdAXGtFSW3uvQTGp3AHlJc3CsdfntqVqPyZKiLT3szKy5ubFdYGszQHbcFJAB3qncJeh7TPLD Q/U3AkplmLHvBmLMwTQvzZoum3ad1AyIyFb5DKJqltj7J4qMTkVxXEKyDA1gevPcKl0CO8G50Zg H4RapFxApmOE5PDEGxENfnN+++YqEd3zQqjPdRe//1HXfPL2gKlCpe+PD7Z2C1Eu8seayucJmEB rlXtspwuA/x5AnsUUn/DAe/qHokTXCHracZ/iH0i08NCoerT5A4Jhowpg2X9wEbXGvZ1lRCb+kD TlPhsZF6892y+3wXPsg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-26_02,2026-03-24_01,2025-10-01_01 On 2026-03-20 at 22:20:37, Simon Horman (horms@kernel.org) wrote: > This is an AI-generated review of your patch. The human sending this > email has considered the AI review valid, or at least plausible. > > For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html > --- > octeontx2-pf: cn20k: Use unified Halo context > > Use unified Halo context present in CN20K hardware for > octeontx2 netdevs instead of aura and pool contexts. > > > diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c b/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c > > --- a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c > > +++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c > > [ ... ] > > > +int cn20k_npa_alloc_dpc(struct otx2_nic *nic) > > +{ > > + struct npa_cn20k_dpc_alloc_req *req; > > + struct npa_cn20k_dpc_alloc_rsp *rsp; > > + int err; > > + > > + req = otx2_mbox_alloc_msg_npa_cn20k_dpc_alloc(&nic->mbox); > > + if (!req) > > + return -ENOMEM; > > + > > + /* Count successful ALLOC requests only */ > > + req->dpc_conf = 1ULL << 4; > > + > > + err = otx2_sync_mbox_msg(&nic->mbox); > > + if (err) > > + return err; > > + > > + rsp = (struct npa_cn20k_dpc_alloc_rsp *)otx2_mbox_get_rsp(&nic->mbox.mbox, > > + 0, &req->hdr); > > + if (IS_ERR(rsp)) > > + return PTR_ERR(rsp); > > + > > + nic->npa_dpc = rsp->cntr_id; > > + > > + return 0; > > +} > > [ ... ] > > > diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c > > --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c > > +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c > > @@ -1651,6 +1651,9 @@ int otx2_init_hw_resources(struct otx2_nic *pf) > > if (!is_otx2_lbkvf(pf->pdev)) > > otx2_nix_config_bp(pf, true); > > > > + if (is_cn20k(pf->pdev)) > > + cn20k_npa_alloc_dpc(pf); > ^^^^^^^^^^^^^^^^^^^^^ > > Should the return value of cn20k_npa_alloc_dpc() be checked here? > DPC counters are for debugging only we can proceed if counter was not allocated. > Looking at cn20k_npa_alloc_dpc(), it can return -ENOMEM or errors from > otx2_sync_mbox_msg() or PTR_ERR() from otx2_mbox_get_rsp(). If the DPC > counter allocation fails, pf->npa_dpc remains 0 (from struct > zero-initialization). > > Then cn20k_halo_aq_init() configures all NPA auras with > aq->halo.op_dpc_set = pfvf->npa_dpc (= 0), referencing an unallocated > DPC performance counter. On teardown, cn20k_npa_free_dpc() sends a mbox > message to free counter ID 0, which was never allocated. Agreed. Will add npa_dpc_valid flag and based on that only will use pfvf->npa_dpc to fix this. Thanks, Sundeep > > Every other error-returning mbox operation in this function checks the > return value and jumps to an error label on failure. Should this follow > the same pattern? > > > + > > /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ > > err = otx2_rq_aura_pool_init(pf); > > if (err) { > > [ ... ]