[PATCH iwl-next] ice: check cross-timestamp timeout bits

[Aleksandr Loktionov <aleksandr.loktionov@intel.com>]

From: Karol Kolacinski <karol.kolacinski@intel.com>

Polling for cross-timestamp active bit depends on HW scheduling and
actual timeout may happen before the driver finishes polling.

Check cross-timestamp timeout bits to ensure that the driver finishes
the operation earlier when HW indicates timeout.

Fixes: 92456e795ac6 ("ice: Add unified ice_capture_crosststamp")
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
---

 drivers/net/ethernet/intel/ice/ice_hw_autogen.h |  3 +++
 drivers/net/ethernet/intel/ice/ice_ptp.c        | 12 ++++++++++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
index 082ad33..8b4884e 100644
--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
@@ -499,6 +499,8 @@
 #define PRTRPB_RDPC				0x000AC260
 #define GLHH_ART_CTL				0x000A41D4
 #define GLHH_ART_CTL_ACTIVE_M			BIT(0)
+#define GLHH_ART_CTL_TIME_OUT1_M		BIT(1)
+#define GLHH_ART_CTL_TIME_OUT2_M		BIT(2)
 #define GLHH_ART_TIME_H				0x000A41D8
 #define GLHH_ART_TIME_L				0x000A41DC
 #define GLTSYN_AUX_IN_0(_i)			(0x000889D8 + ((_i) * 4))
@@ -564,6 +566,7 @@
 #define E830_PRTTSYN_TXTIME_L(_i)		(0x001E5000 + ((_i) * 32))
 #define E830_GLPTM_ART_CTL			0x00088B50
 #define E830_GLPTM_ART_CTL_ACTIVE_M		BIT(0)
+#define E830_GLPTM_ART_CTL_TIME_OUT_M		BIT(1)
 #define E830_GLPTM_ART_TIME_H			0x00088B54
 #define E830_GLPTM_ART_TIME_L			0x00088B58
 #define E830_GLTSYN_PTMTIME_H(_i)		(0x00088B48 + ((_i) * 4))
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c
index 6848b1c..8b0530b 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
@@ -2011,6 +2011,7 @@ static int ice_ptp_adjtime(struct ptp_clock_info *info, s64 delta)
  * @lock_busy: Bit in the semaphore lock indicating the lock is busy
  * @ctl_reg: The hardware register to request cross timestamp
  * @ctl_active: Bit in the control register to request cross timestamp
+ * @ctl_timeout: Bits in the control register to indicate HW timeout
  * @art_time_l: Lower 32-bits of ART system time
  * @art_time_h: Upper 32-bits of ART system time
  * @dev_time_l: Lower 32-bits of device time (per timer index)
@@ -2024,6 +2025,7 @@ struct ice_crosststamp_cfg {
 	/* Capture control register */
 	u32 ctl_reg;
 	u32 ctl_active;
+	u32 ctl_timeout;
 
 	/* Time storage */
 	u32 art_time_l;
@@ -2037,6 +2039,7 @@ static const struct ice_crosststamp_cfg ice_crosststamp_cfg_e82x = {
 	.lock_busy = PFHH_SEM_BUSY_M,
 	.ctl_reg = GLHH_ART_CTL,
 	.ctl_active = GLHH_ART_CTL_ACTIVE_M,
+	.ctl_timeout = GLHH_ART_CTL_TIME_OUT1_M | GLHH_ART_CTL_TIME_OUT2_M,
 	.art_time_l = GLHH_ART_TIME_L,
 	.art_time_h = GLHH_ART_TIME_H,
 	.dev_time_l[0] = GLTSYN_HHTIME_L(0),
@@ -2051,6 +2054,7 @@ static const struct ice_crosststamp_cfg ice_crosststamp_cfg_e830 = {
 	.lock_busy = E830_PFPTM_SEM_BUSY_M,
 	.ctl_reg = E830_GLPTM_ART_CTL,
 	.ctl_active = E830_GLPTM_ART_CTL_ACTIVE_M,
+	.ctl_timeout = E830_GLPTM_ART_CTL_TIME_OUT_M,
 	.art_time_l = E830_GLPTM_ART_TIME_L,
 	.art_time_h = E830_GLPTM_ART_TIME_H,
 	.dev_time_l[0] = E830_GLTSYN_PTMTIME_L(0),
@@ -2123,9 +2127,13 @@ static int ice_capture_crosststamp(ktime_t *device,
 	ctl |= cfg->ctl_active;
 	wr32(hw, cfg->ctl_reg, ctl);
 
-	/* Poll until hardware completes the capture */
-	err = rd32_poll_timeout(hw, cfg->ctl_reg, ctl, !(ctl & cfg->ctl_active),
+	/* Poll until hardware completes the capture or timeout occurs */
+	err = rd32_poll_timeout(hw, cfg->ctl_reg, ctl,
+				!(ctl & cfg->ctl_active) ||
+				(ctl & cfg->ctl_timeout),
 				5, 20 * USEC_PER_MSEC);
+	if (ctl & cfg->ctl_timeout)
+		err = -ETIMEDOUT;
 	if (err)
 		goto err_timeout;
 
-- 
2.52.0