From: Suraj Gupta <suraj.gupta2@amd.com>
To: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S . Miller" <davem@davemloft.net>,
"Eric Dumazet" <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>
Cc: Michal Simek <michal.simek@amd.com>,
Sean Anderson <sean.anderson@linux.dev>,
Daniel Borkmann <daniel@iogearbox.net>,
"Ariane Keller" <ariane.keller@tik.ee.ethz.ch>,
<netdev@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH net V2 0/2] Correct BD length masks and BQL accounting for multi-BD TX packets
Date: Fri, 27 Mar 2026 13:02:36 +0530 [thread overview]
Message-ID: <20260327073238.134948-1-suraj.gupta2@amd.com> (raw)
This patch series fixes two issues in the Xilinx AXI Ethernet driver:
1. Corrects the BD length masks to match the AXIDMA IP spec.
2. Fixes BQL accounting for multi-BD TX packets.
---
Changes in V2:
- Define BD length masks with GENMASK(25, 0) per PG021.
- Credit BQL using skb->len on packet completion instead of summing
per-BD actual lengths from descriptor status.
---
Suraj Gupta (2):
net: xilinx: axienet: Correct BD length masks to match AXIDMA IP spec
net: xilinx: axienet: Fix BQL accounting for multi-BD TX packets
drivers/net/ethernet/xilinx/xilinx_axienet.h | 4 ++--
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 9 ++++-----
2 files changed, 6 insertions(+), 7 deletions(-)
--
2.49.1
next reply other threads:[~2026-03-27 7:32 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-27 7:32 Suraj Gupta [this message]
2026-03-27 7:32 ` [PATCH net V2 1/2] net: xilinx: axienet: Correct BD length masks to match AXIDMA IP spec Suraj Gupta
2026-03-27 7:32 ` [PATCH net V2 2/2] net: xilinx: axienet: Fix BQL accounting for multi-BD TX packets Suraj Gupta
-- strict thread matches above, loose matches on Subject: below --
2026-03-26 18:55 [PATCH net V2 0/2] Correct BD length masks and " Suraj Gupta
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