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R . Silva" , Richard Cochran Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-hardening@vger.kernel.org, netdev@vger.kernel.org, Sia Jee Heng , Hal Feng , Ley Foon Tan , Changhuang Liang Subject: [PATCH v1 08/22] clk: starfive: Add JHB100 System-1 clock generator driver Date: Thu, 2 Apr 2026 03:55:09 -0700 Message-Id: <20260402105523.447523-9-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com> References: <20260402105523.447523-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: ZQ0PR01CA0028.CHNPR01.prod.partner.outlook.cn (10.2.0.210) To ZQ0PR01MB1208.CHNPR01.prod.partner.outlook.cn (10.2.3.165) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1208:EE_|ZQ0PR01MB1096:EE_ X-MS-Office365-Filtering-Correlation-Id: 81107047-b343-4131-909e-08de90a66b41 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|52116014|376014|366016|921020|38350700014|22082099003|18002099003|56012099003; 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Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 8 + drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jhb100-sys1.c | 157 ++++++++++++++++++ 3 files changed, 166 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys1.c diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index 7926e02ccd7d..b6042bcb5992 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -83,3 +83,11 @@ config CLK_STARFIVE_JHB100_SYS0 help Say yes here to support the system-0 clock controller on the StarFive JHB100 SoC. + +config CLK_STARFIVE_JHB100_SYS1 + bool "StarFive JHB100 system-1 clock support" + depends on CLK_STARFIVE_JHB100_SYS0 + default ARCH_STARFIVE + help + Say yes here to support the system-1 clock controller on the + StarFive JHB100 SoC. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index 2c5e66d1d44e..b3571e2f0555 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o +obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys1.c b/drivers/clk/starfive/clk-starfive-jhb100-sys1.c new file mode 100644 index 000000000000..e98b8bc72960 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-sys1.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 System-1 Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + * + */ + +#include +#include +#include +#include +#include + +#include "clk-starfive-jhb100.h" + +#define JHB100_SYS1CLK_NUM_CLKS (JHB100_SYS1CLK_BMCPER3_125 + 1) + +/* external clocks */ +#define JHB100_SYS1CLK_OSC (JHB100_SYS1CLK_NUM_CLKS + 0) +#define JHB100_SYS1CLK_PLL0 (JHB100_SYS1CLK_NUM_CLKS + 1) +#define JHB100_SYS1CLK_PLL1 (JHB100_SYS1CLK_NUM_CLKS + 2) +#define JHB100_SYS1CLK_PLL2 (JHB100_SYS1CLK_NUM_CLKS + 3) +#define JHB100_SYS1CLK_PLL4 (JHB100_SYS1CLK_NUM_CLKS + 4) +#define JHB100_SYS1CLK_PLL5 (JHB100_SYS1CLK_NUM_CLKS + 5) +#define JHB100_SYS1CLK_NPU_600 (JHB100_SYS1CLK_NUM_CLKS + 6) + +static const struct starfive_clk_data jhb100_sys1crg_clk_data[] __initconst = { + /* root */ + STARFIVE__DIV(JHB100_SYS1CLK_APB_MAIN_SYS1, "apb_main_sys1", 12, + JHB100_SYS1CLK_PLL1), + /* sensor */ + STARFIVE_GATE(JHB100_SYS1CLK_APB_SENSOR_ICG_BUF, "apb_sensor_icg_buf", + CLK_IS_CRITICAL, JHB100_SYS1CLK_APB_MAIN_SYS1), + /* hostss1 */ + STARFIVE__DIV(JHB100_SYS1CLK_GPIO_ESPI1_66, "gpio_espi1_66", 14, + JHB100_SYS1CLK_PLL2), + STARFIVE__DIV(JHB100_SYS1CLK_HOSTSS1_100, "hostss1_100", 12, + JHB100_SYS1CLK_PLL1), + STARFIVE_GATE(JHB100_SYS1CLK_HOSTSS1_PHY_SCAN_1000_ICG_BUF, + "hostss1_phy_scan_1000_icg_buf", CLK_IS_CRITICAL, + JHB100_SYS1CLK_PLL1), + /* vout */ + STARFIVE__DIV(JHB100_SYS1CLK_VOUT_100, "vout_100", 12, + JHB100_SYS1CLK_PLL1), + STARFIVE__DIV(JHB100_SYS1CLK_VOUT_PIX0, "vout_pix0", 4, + JHB100_SYS1CLK_PLL4), + STARFIVE__DIV(JHB100_SYS1CLK_VOUT_PIX1, "vout_pix1", 4, + JHB100_SYS1CLK_PLL5), + /* bmcperiph3 */ + STARFIVE__DIV(JHB100_SYS1CLK_BMCPER3_100, "bmcper3_100", 12, + JHB100_SYS1CLK_PLL1), + STARFIVE__DIV(JHB100_SYS1CLK_BMCPER3_125, "bmcper3_125", 10, + JHB100_SYS1CLK_PLL1), + /* npu */ + STARFIVE__DIV(JHB100_SYS1CLK_NPU_200, "npu_200", 6, + JHB100_SYS1CLK_PLL1), + STARFIVE__DIV(JHB100_SYS1CLK_NPU_CORE_DIV, "npu_core_div", 10, + JHB100_SYS1CLK_PLL0), + STARFIVE_GATE(JHB100_SYS1CLK_DOM_NPU_CORE_CLK, "dom_npu_core_clk", + CLK_IS_CRITICAL, JHB100_SYS1CLK_NPU_CORE_DIV), + STARFIVE_GATE(JHB100_SYS1CLK_DOM_NPU_BUS_CLK, "dom_npu_bus_clk", + CLK_IS_CRITICAL, JHB100_SYS1CLK_NPU_600), + STARFIVE_GATE(JHB100_SYS1CLK_DOM_NPU_INIT_CLK, "dom_npu_init_clk", + CLK_IS_CRITICAL, JHB100_SYS1CLK_NPU_200), + STARFIVE_GATE(JHB100_SYS1CLK_DOM_NPU_OSC_CLK, "dom_npu_osc_clk", + CLK_IS_CRITICAL, JHB100_SYS1CLK_OSC), +}; + +static int __init jhb100_sys1crg_probe(struct platform_device *pdev) +{ + struct starfive_clk_priv *priv; + unsigned int idx; + int ret; + + priv = devm_kzalloc(&pdev->dev, + struct_size(priv, reg, JHB100_SYS1CLK_NUM_CLKS), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + spin_lock_init(&priv->rmw_lock); + priv->num_reg = JHB100_SYS1CLK_NUM_CLKS; + priv->dev = &pdev->dev; + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + for (idx = 0; idx < JHB100_SYS1CLK_NUM_CLKS; idx++) { + u32 max = jhb100_sys1crg_clk_data[idx].max; + struct clk_parent_data parents[4] = {}; + struct clk_init_data init = { + .name = jhb100_sys1crg_clk_data[idx].name, + .ops = starfive_clk_ops(max), + .parent_data = parents, + .num_parents = + ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1, + .flags = jhb100_sys1crg_clk_data[idx].flags, + }; + struct starfive_clk *clk = &priv->reg[idx]; + unsigned int i; + + if (!init.name) + continue; + + for (i = 0; i < init.num_parents; i++) { + unsigned int pidx = jhb100_sys1crg_clk_data[idx].parents[i]; + + if (pidx < JHB100_SYS1CLK_NUM_CLKS) + parents[i].hw = &priv->reg[pidx].hw; + else if (pidx == JHB100_SYS1CLK_OSC) + parents[i].fw_name = "osc"; + else if (pidx == JHB100_SYS1CLK_PLL0) + parents[i].fw_name = "pll0"; + else if (pidx == JHB100_SYS1CLK_PLL1) + parents[i].fw_name = "pll1"; + else if (pidx == JHB100_SYS1CLK_PLL2) + parents[i].fw_name = "pll2"; + else if (pidx == JHB100_SYS1CLK_PLL4) + parents[i].fw_name = "pll4"; + else if (pidx == JHB100_SYS1CLK_PLL5) + parents[i].fw_name = "pll5"; + else + parents[i].fw_name = "sys1_npu_600"; + } + + clk->hw.init = &init; + clk->idx = idx; + clk->max_div = max & STARFIVE_CLK_DIV_MASK; + + ret = devm_clk_hw_register(&pdev->dev, &clk->hw); + if (ret) + return ret; + } + + ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv); + if (ret) + return ret; + + return jhb100_reset_controller_register(priv, "r-sys1", 0); +} + +static const struct of_device_id jhb100_sys1crg_match[] = { + { .compatible = "starfive,jhb100-sys1crg" }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_sys1crg_driver = { + .driver = { + .name = "clk-starfive-jhb100-sys1", + .of_match_table = jhb100_sys1crg_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver_probe(jhb100_sys1crg_driver, jhb100_sys1crg_probe); -- 2.25.1