From: Prathamesh Deshpande <prathameshdeshpande7@gmail.com>
To: cjubran@nvidia.com
Cc: leon@kernel.org, linux-kernel@vger.kernel.org,
linux-rdma@vger.kernel.org, mbloch@nvidia.com,
netdev@vger.kernel.org, prathameshdeshpande7@gmail.com,
richardcochran@gmail.com, saeedm@nvidia.com, tariqt@nvidia.com
Subject: Re: [PATCH v2] net/mlx5: Fix OOB access and stack information leak in
Date: Fri, 10 Apr 2026 03:00:25 +0100 [thread overview]
Message-ID: <20260410020025.7386-1-prathameshdeshpande7@gmail.com> (raw)
In-Reply-To: <3a238d0c-4ec1-432d-995a-19d7db3e310e@nvidia.com>
On Thu, Apr 9, 2026 at 17:16 +0300, Carolina Jubran wrote:
> pin is defined as u8 in struct mlx5_eqe_pps, so pin < 0 is dead code.
>
> As for the upper bound: in order to receive a PPS event on a pin, the
> user must first configure it via mlx5_ptp_enable, which already
> validates the index (rq->extts.index >= clock->ptp_info.n_pins returns
> -EINVAL) and since the mtpps register only defines capabilities for 8
> pins, so n_pins cannot exceed MAX_PIN_NUM.
>
> Maybe wrap it with WARN_ON_ONCE instead of silently returning, so if
> future hardware adds support for more pins we would notice rather than
> silently dropping events.
Hi Carolina,
Thanks for the feedback. I've removed the redundant pin < 0 check and
implemented the WARN_ON_ONCE for the upper bound as suggested.
I just submitted a v3 as a fresh thread with these changes and a fix
for the union corruption bug.
Thanks,
Prathamesh
prev parent reply other threads:[~2026-04-10 2:00 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-31 15:31 [PATCH] net/mlx5: Fix potential NULL dereference in PTP event handling Prathamesh Deshpande
2026-04-02 0:30 ` [PATCH v2] net/mlx5: Fix OOB access and stack information leak " Prathamesh Deshpande
2026-04-09 13:54 ` Carolina Jubran
2026-04-09 13:58 ` Carolina Jubran
2026-04-09 14:07 ` Carolina Jubran
2026-04-09 14:10 ` Carolina Jubran
2026-04-09 14:16 ` Carolina Jubran
2026-04-10 2:00 ` Prathamesh Deshpande [this message]
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