[PATCH v2 5/6] bus: mhi: host: Update the Time sync logic to read 64 bit register value

Krishna Chaitanya Chundru
2026-04-11T08:12:28Z

Instead of reading low and high of the mhi registers twice use 64 bit
register value to avoid any time penality.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
drivers/bus/mhi/host/main.c | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c
index 99917593e1da06f1dece7b5b0037c2485953410f..e853419a0195dff4a18123631cb1f74242ab4428 100644
--- a/drivers/bus/mhi/host/main.c
+++ b/drivers/bus/mhi/host/main.c
@@ -1643,6 +1643,7 @@ static int mhi_get_remote_time(struct mhi_controller *mhi_cntrl, struct mhi_time
struct mhi_timesync_info *time)
{
struct device *dev = &mhi_cntrl->mhi_dev->dev;
+ u64 val = U64_MAX;
int ret, i;

if (!mhi_tsync && !mhi_tsync->time_reg) {
@@ -1680,15 +1681,25 @@ static int mhi_get_remote_time(struct mhi_controller *mhi_cntrl, struct mhi_time
* transition to L0.
*/
for (i = 0; i < MHI_NUM_BACK_TO_BACK_READS; i++) {
- ret = mhi_read_reg(mhi_cntrl, mhi_tsync->time_reg,
- TSC_TIMESYNC_TIME_LOW_OFFSET, &time->t_dev_lo);
-
- ret = mhi_read_reg(mhi_cntrl, mhi_tsync->time_reg,
- TSC_TIMESYNC_TIME_HIGH_OFFSET, &time->t_dev_hi);
+ if (mhi_cntrl->read_reg64) {
+ ret = mhi_read_reg64(mhi_cntrl, mhi_tsync->time_reg,
+ TSC_TIMESYNC_TIME_LOW_OFFSET, &val);
+ } else {
+ ret = mhi_read_reg(mhi_cntrl, mhi_tsync->time_reg,
+ TSC_TIMESYNC_TIME_LOW_OFFSET, &time->t_dev_lo);
+
+ ret = mhi_read_reg(mhi_cntrl, mhi_tsync->time_reg,
+ TSC_TIMESYNC_TIME_HIGH_OFFSET, &time->t_dev_hi);
+ }
}

time->t_host_post = ktime_get_real();

+ if (mhi_cntrl->read_reg64) {
+ time->t_dev_lo = (u32)val;
+ time->t_dev_hi = (u32)(val >> 32);
+ }
+
local_irq_enable();
preempt_enable();

--
2.34.1