Re: [PATCH v5 net-next 4/8] dpll: zl3073x: allow SyncE_Ref pin state change

Ivan Vecera
2026-04-08T09:45:03Z

On 4/3/26 1:06 AM, Grzegorz Nitka wrote:
> The SyncE_Ref pin may operate as either an active or inactive reference
> depending on board design and system configuration. Some platforms need
> to disable the SyncE reference dynamically (e.g., when selecting a
> different recovered clock input). The hardware supports toggling this
> pin, therefore advertise the STATE_CAN_CHANGE capability.
>
> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
> ---
> drivers/dpll/zl3073x/prop.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/dpll/zl3073x/prop.c b/drivers/dpll/zl3073x/prop.c
> index ac9d41d0f978..acd7061a741a 100644
> --- a/drivers/dpll/zl3073x/prop.c
> +++ b/drivers/dpll/zl3073x/prop.c
> @@ -215,6 +215,15 @@ struct zl3073x_pin_props *zl3073x_pin_props_get(struct zl3073x_dev *zldev,
>
> props->dpll_props.type = DPLL_PIN_TYPE_GNSS;
>
> + /*
> + * The SyncE_Ref pin supports enabling/disabling dynamically.
> + * Some platforms may choose to expose this through firmware
> + * configuration later. For now, advertise this capability
> + * universally since the hardware allows state toggling.
> + */
> + props->dpll_props.capabilities |=
> + DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
> +
> /* The output pin phase adjustment granularity equals half of
> * the synth frequency count.
> */
Reviewed-by: Ivan Vecera <ivecera@redhat.com>