From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 197033D564B for ; Wed, 15 Apr 2026 14:28:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776263334; cv=none; b=nETtJFC05yoHco+zF6yFSPTIvdYRFgIRzfdJh4QzxDKZkVK+1gT4Hgvl0HCX5715yc7mb/DVZ4MCKJC76t9gL+o6znL9IdUJm4SgrmNJiqIBhXPDlNKzy4D5trtugj3nexvW+73TkOGtgz/MSDpnC2z/RRtn6fmOfCFrU4i+Fco= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776263334; c=relaxed/simple; bh=KqWXBLN1y2tBAU5MfQdxigjBV0ykVvzEk82ODCrBxvE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=S6Sj/Mem9Y51lM7zpGz2CT9/fW9sHSFuBg1ch9OBsUU+761RDOXyL0cphkOw4ch+HvRr6mGPsQOo7a+fmwATe2uTKdvqC/2XyEptEbWuA4DNjoXS4X8fZSBhl644djG1T+gnhpltLn3ALgIDrUdKh/4HY/5fMFAk/noL1y0vtXw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WFTOA1zJ; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WFTOA1zJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776263333; x=1807799333; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KqWXBLN1y2tBAU5MfQdxigjBV0ykVvzEk82ODCrBxvE=; b=WFTOA1zJr8SNk8kXL5sI0hkr6g4Mzo5GngMD/aa1RhUn8XBUQYuBManT EKvGO/G8V/2VUBZDn9wGVWr+omIgjbbCfuHJzYaxYDrRuMfpzIdbhL7Ho c3H5Zgq7c2XT8OqFpHYU4ITrZVNSFSbMyGLDAl3xR+9eTvTwOxTm2CZXl ZqKayf7doY84Xsw3H4eo1S7P3vBHkd4JwfRPsU2tCpNYGxnh3b3xAo3fY oC4+EFjq/thTGE6EROAF4ybIPm8dLgrKBeqwCLI4VMTKTy/4uO13DE2u+ LlEHa2R0CgUeeXqA8VtU+c7wpbCCfTlo5CY0uyh+BuTinSpjzF4ADCRF5 g==; X-CSE-ConnectionGUID: lw5CoDvAQmCjzxYUpuWTMQ== X-CSE-MsgGUID: 5iZdzBKyQP2sLK1+eeHJfA== X-IronPort-AV: E=McAfee;i="6800,10657,11760"; a="77423745" X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="77423745" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2026 07:28:51 -0700 X-CSE-ConnectionGUID: 4umZa15tQv22yAIkuPCDRQ== X-CSE-MsgGUID: DtpY65ZfSrGKTtIAJzAdfg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,179,1770624000"; d="scan'208";a="234467884" Received: from amlin-019-225.igk.intel.com ([10.102.19.225]) by orviesa003.jf.intel.com with ESMTP; 15 Apr 2026 07:28:50 -0700 From: Aleksandr Loktionov To: intel-wired-lan@lists.osuosl.org, anthony.l.nguyen@intel.com, aleksandr.loktionov@intel.com Cc: netdev@vger.kernel.org Subject: [PATCH iwl-net v3 5/6] ixgbe: fix ITR value overflow in adaptive interrupt throttling Date: Wed, 15 Apr 2026 16:28:40 +0200 Message-ID: <20260415142841.3222399-6-aleksandr.loktionov@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260415142841.3222399-1-aleksandr.loktionov@intel.com> References: <20260415142841.3222399-1-aleksandr.loktionov@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit ixgbe_update_itr() packs a mode flag (IXGBE_ITR_ADAPTIVE_LATENCY, bit 7) and a usecs delay (bits [6:0]) into an unsigned int, then stores the combined value in ring_container->itr which is declared as u8. Values above 0xFF wrap on truncation, corrupting both the delay and the mode flag on the next readback. Keep the mode bit (IXGBE_ITR_ADAPTIVE_LATENCY) and the usec delay as separate operands in the final store expression. Clamp only the usecs portion to [IXGBE_ITR_ADAPTIVE_MIN_USECS, IXGBE_ITR_ADAPTIVE_MAX_USECS] using clamp_val() so that: - overflow cannot bleed into the mode bit (bit 7), - the delay cannot exceed 126 us (IXGBE_ITR_ADAPTIVE_MAX_USECS), - the delay cannot drop below 10 us (IXGBE_ITR_ADAPTIVE_MIN_USECS). Fixes: b4ded8327fea ("ixgbe: Update adaptive ITR algorithm") Cc: stable@vger.kernel.org Signed-off-by: Aleksandr Loktionov --- v2 -> v3: - Use clamp_val() instead of min_t() to also guard the lower bound (IXGBE_ITR_ADAPTIVE_MIN_USECS); keep mode and delay as separate operands until final store; use IXGBE_ITR_ADAPTIVE_MAX_USECS (126) as upper bound instead of IXGBE_ITR_ADAPTIVE_LATENCY - 1 (127) (Simon Horman). v1 -> v2: - Add proper [N/M] numbering so patchwork tracks it as part of the set; no code change. drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 10 +++++++--- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c index 210c7b9..9f3ae21 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c @@ -2886,11 +2886,17 @@ static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * IXGBE_ITR_ADAPTIVE_MIN_INC; break; } clear_counts: - /* write back value */ - ring_container->itr = itr; + /* Separate mode bit (IXGBE_ITR_ADAPTIVE_LATENCY) from usec delay; + * clamp delay to [MIN_USECS, MAX_USECS] before storing to prevent + * u8 truncation from corrupting the mode flag or delay on readback. + */ + ring_container->itr = (itr & IXGBE_ITR_ADAPTIVE_LATENCY) | + clamp_val(itr & ~IXGBE_ITR_ADAPTIVE_LATENCY, + IXGBE_ITR_ADAPTIVE_MIN_USECS, + IXGBE_ITR_ADAPTIVE_MAX_USECS); /* next update should occur within next jiffy */ ring_container->next_update = next_update + 1; -- 2.52.0