[PATCH v2 1/2] dt-bindings: pinctrl: describe the Qualcomm nord-tlmm

Bartosz Golaszewski
2026-04-27T14:00:47Z

Add a DT binding document describing the TLMM pin controller available
on the Nord platforms from Qualcomm.

Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
.../bindings/pinctrl/qcom,nord-tlmm.yaml | 184 +++++++++++++++++++++
1 file changed, 184 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..b776dd20e15b6cfd3d99c7b96cf23733ada817bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml
@@ -0,0 +1,184 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,nord-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SA8797P TLMM block
+
+maintainers:
+ - Bartosz Golaszewski <brgl@kernel.org>
+
+description:
+ Top Level Mode Multiplexer pin controller in Qualcomm SA8797P SoC.
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,nord-tlmm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ gpio-reserved-ranges:
+ minItems: 1
+ maxItems: 90
+
+ gpio-line-names:
+ maxItems: 181
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-nord-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-nord-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-nord-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|180)$"
+ - enum: [ ufs_reset ]
+ minItems: 1
+ maxItems: 16
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ aoss_cti, atest_char0, atest_char1, atest_char2, atest_char3,
+ atest_char_start, atest_usb20, atest_usb21, aud_intfc0_clk,
+ aud_intfc0_data0, aud_intfc0_data1, aud_intfc0_data2,
+ aud_intfc0_data3, aud_intfc0_data4, aud_intfc0_data5,
+ aud_intfc0_data6, aud_intfc0_data7, aud_intfc0_ws,
+ aud_intfc10_clk, aud_intfc10_data0, aud_intfc10_data1,
+ aud_intfc10_ws, aud_intfc1_clk, aud_intfc1_data0,
+ aud_intfc1_data1, aud_intfc1_data2, aud_intfc1_data3,
+ aud_intfc1_data4, aud_intfc1_data5, aud_intfc1_data6,
+ aud_intfc1_data7, aud_intfc1_ws, aud_intfc2_clk,
+ aud_intfc2_data0, aud_intfc2_data1, aud_intfc2_data2,
+ aud_intfc2_data3, aud_intfc2_ws, aud_intfc3_clk,
+ aud_intfc3_data0, aud_intfc3_data1, aud_intfc3_ws,
+ aud_intfc4_clk, aud_intfc4_data0, aud_intfc4_data1,
+ aud_intfc4_ws, aud_intfc5_clk, aud_intfc5_data0,
+ aud_intfc5_data1, aud_intfc5_ws, aud_intfc6_clk,
+ aud_intfc6_data0, aud_intfc6_data1, aud_intfc6_ws,
+ aud_intfc7_clk, aud_intfc7_data0, aud_intfc7_data1,
+ aud_intfc7_ws, aud_intfc8_clk, aud_intfc8_data0,
+ aud_intfc8_data1, aud_intfc8_ws, aud_intfc9_clk,
+ aud_intfc9_data0, aud_intfc9_ws, aud_mclk0_mira,
+ aud_mclk0_mirb, aud_mclk1_mira, aud_mclk1_mirb,
+ aud_mclk2_mira, aud_mclk2_mirb, aud_refclk0, aud_refclk1,
+ bist_done, ccu_async_in0, ccu_async_in1, ccu_async_in2,
+ ccu_async_in3, ccu_async_in4, ccu_async_in5, ccu_i2c_scl0,
+ ccu_i2c_scl1, ccu_i2c_scl2, ccu_i2c_scl3, ccu_i2c_scl4,
+ ccu_i2c_scl5, ccu_i2c_scl6, ccu_i2c_scl7, ccu_i2c_scl8,
+ ccu_i2c_scl9, ccu_i2c_sda0, ccu_i2c_sda1, ccu_i2c_sda2,
+ ccu_i2c_sda3, ccu_i2c_sda4, ccu_i2c_sda5, ccu_i2c_sda6,
+ ccu_i2c_sda7, ccu_i2c_sda8, ccu_i2c_sda9, ccu_timer0,
+ ccu_timer1, ccu_timer10, ccu_timer11, ccu_timer12, ccu_timer13,
+ ccu_timer14, ccu_timer15, ccu_timer2, ccu_timer3, ccu_timer4,
+ ccu_timer5, ccu_timer6, ccu_timer7, ccu_timer8, ccu_timer9,
+ clink_debug, dbg_out, dbg_out_clk, ddr_bist_complete,
+ ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0,
+ ddr_pxi1, ddr_pxi10, ddr_pxi11, ddr_pxi12, ddr_pxi13, ddr_pxi14,
+ ddr_pxi15, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, ddr_pxi6,
+ ddr_pxi7, ddr_pxi8, ddr_pxi9, dp_rx0, dp_rx00, dp_rx01,
+ dp_rx0_mute, dp_rx1, dp_rx10, dp_rx11, dp_rx1_mute, edp0_hot,
+ edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, edp3_hot,
+ edp3_lcd, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3,
+ emac0_mdc, emac0_mdio, emac0_ptp, emac1_mcg0, emac1_mcg1,
+ emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio, emac1_ptp,
+ gcc_gp1_clk, gcc_gp2_clk, gcc_gp3_clk, gcc_gp4_clk, gcc_gp5_clk,
+ gcc_gp6_clk, gcc_gp7_clk, gcc_gp8_clk, jitter_bist, lbist_pass,
+ mbist_pass, mdp0_vsync0_out, mdp0_vsync10_out, mdp0_vsync1_out,
+ mdp0_vsync2_out, mdp0_vsync3_out, mdp0_vsync4_out,
+ mdp0_vsync5_out, mdp0_vsync6_out, mdp0_vsync7_out,
+ mdp0_vsync8_out, mdp0_vsync9_out, mdp1_vsync0_out,
+ mdp1_vsync10_out, mdp1_vsync1_out, mdp1_vsync2_out,
+ mdp1_vsync3_out, mdp1_vsync4_out, mdp1_vsync5_out,
+ mdp1_vsync6_out, mdp1_vsync7_out, mdp1_vsync8_out,
+ mdp1_vsync9_out, mdp_vsync_e, mdp_vsync_p, mdp_vsync_s,
+ pcie0_clk_req_n, pcie1_clk_req_n, pcie2_clk_req_n,
+ pcie3_clk_req_n, phase_flag0, phase_flag1, phase_flag10,
+ phase_flag11, phase_flag12, phase_flag13, phase_flag14,
+ phase_flag15, phase_flag16, phase_flag17, phase_flag18,
+ phase_flag19, phase_flag2, phase_flag20, phase_flag21,
+ phase_flag22, phase_flag23, phase_flag24, phase_flag25,
+ phase_flag26, phase_flag27, phase_flag28, phase_flag29,
+ phase_flag3, phase_flag30, phase_flag31, phase_flag4,
+ phase_flag5, phase_flag6, phase_flag7, phase_flag8,
+ phase_flag9, pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
+ pwrbrk_i_n, qdss_cti, qdss_gpio, qdss_gpio0, qdss_gpio1,
+ qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
+ qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5,
+ qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, qspi0, qspi1,
+ qspi2, qspi3, qspi_clk, qspi_cs0_n, qspi_cs1_n,
+ qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5,
+ qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5,
+ qup1_se6,
+ qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4, qup2_se5,
+ qup2_se6,
+ qup3_se0_mira, qup3_se0_mirb,
+ sailss_ospi, sdc4_clk, sdc4_cmd, sdc4_data, smb_alert,
+ smb_alert_n, smb_clk, smb_dat, tb_trig_sdc4, tmess_prng0,
+ tmess_prng1, tsc_timer0, tsc_timer1, tsc_timer2, tsc_timer3,
+ tsc_timer4, tsc_timer5, tsc_timer6, tsc_timer7, tsc_timer8,
+ tsc_timer9, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
+ tsense_pwm5, tsense_pwm6, tsense_pwm7, tsense_pwm8, usb0_hs,
+ usb0_phy_ps, usb1_hs, usb1_phy_ps, usb2_hs, usxgmii0_phy,
+ usxgmii1_phy, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl]
+
+ required:
+ - pins
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,nord-tlmm";
+ reg = <0x0f100000 0xc0000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 181>;
+ wakeup-parent = <&pdc>;
+
+ qup_uart15_default: qup-uart15-default-state {
+ pins = "gpio147", "gpio148";
+ function = "qup2_se2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+...

--
2.47.3