From: Grzegorz Nitka <grzegorz.nitka@intel.com>
To: netdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, intel-wired-lan@lists.osuosl.org,
poros@redhat.com, richardcochran@gmail.com,
andrew+netdev@lunn.ch, przemyslaw.kitszel@intel.com,
anthony.l.nguyen@intel.com, Prathosh.Satish@microchip.com,
ivecera@redhat.com, jiri@resnulli.us,
arkadiusz.kubalewski@intel.com, vadim.fedorenko@linux.dev,
donald.hunter@gmail.com, horms@kernel.org, pabeni@redhat.com,
kuba@kernel.org, davem@davemloft.net, edumazet@google.com,
Grzegorz Nitka <grzegorz.nitka@intel.com>
Subject: [PATCH v7 net-next 1/8] dpll: add generic DPLL type
Date: Thu, 30 Apr 2026 11:42:31 +0200 [thread overview]
Message-ID: <20260430094238.987976-2-grzegorz.nitka@intel.com> (raw)
In-Reply-To: <20260430094238.987976-1-grzegorz.nitka@intel.com>
Add DPLL_TYPE_GENERIC to represent DPLL devices which do not fit the
existing PPS or EEC classes.
The UAPI type is intentionally generic. During netdev discussion,
maintainers pointed out that introducing identifiers tied to a specific
placement or single design does not scale across ASICs and vendors.
The role of a DPLL is already inferable from the spawning driver,
bus device, and pin topology, without encoding additional
purpose-specific taxonomy in the type name.
Using a generic type keeps the UAPI extensible and avoids premature
naming that may become incorrect as new hardware topologies are
exposed through the DPLL subsystem.
Expose the new type through UAPI and netlink specification as "generic".
Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
---
Documentation/netlink/specs/dpll.yaml | 3 +++
drivers/dpll/dpll_nl.c | 2 +-
include/uapi/linux/dpll.h | 2 ++
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/specs/dpll.yaml
index 40465a3d7fc2..572cf7ae5f36 100644
--- a/Documentation/netlink/specs/dpll.yaml
+++ b/Documentation/netlink/specs/dpll.yaml
@@ -138,6 +138,9 @@ definitions:
-
name: eec
doc: dpll drives the Ethernet Equipment Clock
+ -
+ name: generic
+ doc: generic dpll type for devices outside PPS/EEC classes
render-max: true
-
type: enum
diff --git a/drivers/dpll/dpll_nl.c b/drivers/dpll/dpll_nl.c
index 1e652340a5d7..9a3b70ea3ae0 100644
--- a/drivers/dpll/dpll_nl.c
+++ b/drivers/dpll/dpll_nl.c
@@ -34,7 +34,7 @@ const struct nla_policy dpll_reference_sync_nl_policy[DPLL_A_PIN_STATE + 1] = {
static const struct nla_policy dpll_device_id_get_nl_policy[DPLL_A_TYPE + 1] = {
[DPLL_A_MODULE_NAME] = { .type = NLA_NUL_STRING, },
[DPLL_A_CLOCK_ID] = { .type = NLA_U64, },
- [DPLL_A_TYPE] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
+ [DPLL_A_TYPE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
};
/* DPLL_CMD_DEVICE_GET - do */
diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h
index 871685f7c353..648553053cd8 100644
--- a/include/uapi/linux/dpll.h
+++ b/include/uapi/linux/dpll.h
@@ -109,10 +109,12 @@ enum dpll_clock_quality_level {
* enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute
* @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal
* @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock
+ * @DPLL_TYPE_GENERIC: generic dpll type for devices outside PPS/EEC classes
*/
enum dpll_type {
DPLL_TYPE_PPS = 1,
DPLL_TYPE_EEC,
+ DPLL_TYPE_GENERIC,
/* private: */
__DPLL_TYPE_MAX,
--
2.39.3
next prev parent reply other threads:[~2026-04-30 9:46 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-30 9:42 [PATCH v7 net-next 0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825 Grzegorz Nitka
2026-04-30 9:42 ` Grzegorz Nitka [this message]
2026-04-30 11:49 ` [Intel-wired-lan] [PATCH v7 net-next 1/8] dpll: add generic DPLL type Loktionov, Aleksandr
2026-05-05 7:43 ` Nitka, Grzegorz
2026-04-30 9:42 ` [PATCH v7 net-next 2/8] dpll: allow registering FW-identified pin with a different DPLL Grzegorz Nitka
2026-05-02 17:27 ` Jakub Kicinski
2026-05-05 8:59 ` Nitka, Grzegorz
2026-04-30 9:42 ` [PATCH v7 net-next 3/8] dpll: extend pin notifier and netlink events with notification source ID Grzegorz Nitka
2026-05-02 17:29 ` Jakub Kicinski
2026-05-02 17:31 ` Jakub Kicinski
2026-04-30 9:42 ` [PATCH v7 net-next 4/8] dpll: zl3073x: allow SyncE_Ref pin state change Grzegorz Nitka
2026-05-02 17:33 ` Jakub Kicinski
2026-04-30 9:42 ` [PATCH v7 net-next 5/8] ice: introduce TXC DPLL device and TX ref clock pin framework for E825 Grzegorz Nitka
2026-04-30 11:46 ` [Intel-wired-lan] " Loktionov, Aleksandr
2026-05-02 17:33 ` Jakub Kicinski
2026-05-05 21:33 ` Nitka, Grzegorz
2026-04-30 9:42 ` [PATCH v7 net-next 6/8] ice: implement CPI support for E825C Grzegorz Nitka
2026-05-02 17:33 ` Jakub Kicinski
2026-04-30 9:42 ` [PATCH v7 net-next 7/8] ice: add Tx reference clock index handling to AN restart command Grzegorz Nitka
2026-04-30 11:29 ` [Intel-wired-lan] " Loktionov, Aleksandr
2026-04-30 9:42 ` [PATCH v7 net-next 8/8] ice: implement E825 TX ref clock control and TXC hardware sync status Grzegorz Nitka
2026-04-30 11:33 ` [Intel-wired-lan] " Loktionov, Aleksandr
2026-04-30 11:37 ` Loktionov, Aleksandr
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