From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E33BA3DFC82; Mon, 4 May 2026 14:24:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777904663; cv=none; b=ZB8/d8Ms4MaLFUBoBqICiBMVI8jVjTPxSnLXFehgVvCY2wbWTMkuKVpWXc9ccI1v0YIM9XoGzNArySIZG/VPgtoiYAwLS9UFFA4G8UX4As7U8UrdxXSykzbbZP0/rHRgGkzkj6G4IajjCsZDf0zcisA0n3aad6Ndmg/DZAP5vV8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777904663; c=relaxed/simple; bh=pLLUnpsQHk0XLLoB+wBplrU8A7WIjOzUca/wCfOw6mw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=mlAnbmXaVg9LQa7ruHLF5B5heecpnXojBQaHugx5ipYNgq22JnKMkwvmhY7loxNTIa/YL9Z/eBE0IDkLyfvpmaecpbcrTd9nv3QZRxuAKh1hN4vo2YNhxn+yPGpMjnhLZqiamENVUxch8Egbkfk9anLReJ9Dqdb4895+45iJ33M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=qHFTnYeV; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="qHFTnYeV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1777904662; x=1809440662; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=pLLUnpsQHk0XLLoB+wBplrU8A7WIjOzUca/wCfOw6mw=; b=qHFTnYeVaIGuAqoQ3CVqhcwu/J886V3R5/cP8YjM6l9PNETMsLYAPu7W JnpjBPdg8OQ3Qn61Hzwb55hm7uo3WbJDrK2t6/P5ddqVkzALPdIgSUtHm KHVHPwSmah/BXGPfJuXxDDTHh4aW5/q/6mzsTimGtikW8M4GjaC7PNxmm vZMb1ZA6ObFvFBpSlSVeTrJq+WWFFvANx4h25uTGvYf5uqMFVW9vB2KU+ DheAmXtPw6Kx5dhXOIS5zzfZVIt+Q/tvc13V6F9NAu8oJh0KbjHbnE5dQ vmlMuOxPlK/9skOicP3yJeK2ZZG8/8zX9SiF9Tt0v94Z7xXiBsnSND+vV w==; X-CSE-ConnectionGUID: XLVlPWwuROO42O1GHZXvZA== X-CSE-MsgGUID: QYF/9F5KSwOcNVPsd9exow== X-IronPort-AV: E=Sophos;i="6.23,215,1770620400"; d="scan'208";a="57408637" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2026 07:24:21 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.87.71) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Mon, 4 May 2026 07:24:20 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 4 May 2026 07:24:17 -0700 From: Daniel Machon Date: Mon, 4 May 2026 16:23:25 +0200 Subject: [PATCH net-next v3 12/13] misc: lan966x-pci: dts: extend cpu reg to cover PCIE DBI space Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260504-lan966x-pci-fdma-v3-12-a56f5740d870@microchip.com> References: <20260504-lan966x-pci-fdma-v3-0-a56f5740d870@microchip.com> In-Reply-To: <20260504-lan966x-pci-fdma-v3-0-a56f5740d870@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: , , , X-Mailer: b4 0.14.3 The ATU outbound windows used by the FDMA engine are programmed through registers at offset 0x400000+, which falls outside the current cpu reg mapping. Extend the cpu reg size from 0x100000 (1MB) to 0x800000 (8MB) to cover the full PCIE DBI and iATU register space. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/misc/lan966x_pci.dtso | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/lan966x_pci.dtso b/drivers/misc/lan966x_pci.dtso index 7b196b0a0eb6..7bb726550caf 100644 --- a/drivers/misc/lan966x_pci.dtso +++ b/drivers/misc/lan966x_pci.dtso @@ -135,7 +135,7 @@ lan966x_phy1: ethernet-lan966x_phy@2 { switch: switch@e0000000 { compatible = "microchip,lan966x-switch"; - reg = <0xe0000000 0x0100000>, + reg = <0xe0000000 0x0800000>, <0xe2000000 0x0800000>; reg-names = "cpu", "gcb"; -- 2.34.1