From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 191EE3E51D3 for ; Mon, 4 May 2026 14:24:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777904699; cv=none; b=MbKQYQ17GrlB4Kq19ORgCFQqw6jWhPAaF5p5ogea9ggV32pduLHZr2bpYnWWXJRgA/i7rHKlgsj3CT8mibFGKdHlMM/2rCNrcLAhL11KlYJeArBGEb59MxYMwFqc26hW0R4uR0dZIKRrh78G+VoaTw66ZADMQd6FmGuZofiS/lY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777904699; c=relaxed/simple; bh=iMyBM89b2seTFG8wKFYplgNuifzMOqRBwqYX3WhqWOE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jmBGtx8nk1YMJs2EMM66f1jLpEALOsmKfqpnumRR6OgQJd8vVPNWnTsSy4q7Po2Rot5KwxNlD39UEZ1OF7UKI4oUwoUpgoarGbJQ6Ro3iTulzpDoNzqdZK2jb5X7lM/498jruHEdfTCUl6r2c8BPmAYAAzMFcatsKVhqEgtTG4I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=k0w0oA92; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="k0w0oA92" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777904698; x=1809440698; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iMyBM89b2seTFG8wKFYplgNuifzMOqRBwqYX3WhqWOE=; b=k0w0oA92KuZjPFz/NDhcygtx82FnZo3v89TqPUhOtuddlZ60dvOuc19p MEpFMhOIUDAKqDNqv0Fl78ty+nzb57LmcOiwcrdNKTgnOcsfFBjEvOj0N B3Bqh2kNjhsH/xy6P09FhhS0/AbWZOjiGtkcXTmzdCw0cPqKGnve6PXE8 RINFcbbK9G/hjXgWLBwPKmt7HNADEpEgNSpC2obCpn0OSdIbHsq6XifAA qE9cR89+QtLqzAbdzhKVjtbXvBk1Uhspmv8fvk/m+PxC+FmrQQWS48bOg 0fh+4teu/+k2Kk5CFA6tmSYTU81cuhM5szyn19uKoxS8dIqOAgHUeBNI4 Q==; X-CSE-ConnectionGUID: 7rKq0HxeS7iLoJwwGSp5UA== X-CSE-MsgGUID: ZFDlL+dhTDq8N+Txrh43ww== X-IronPort-AV: E=McAfee;i="6800,10657,11776"; a="78691611" X-IronPort-AV: E=Sophos;i="6.23,215,1770624000"; d="scan'208";a="78691611" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2026 07:24:58 -0700 X-CSE-ConnectionGUID: CCyCOAddQJyrHO1XXk2bxA== X-CSE-MsgGUID: qH0jbBvtTtu1aOMlkWlc0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,215,1770624000"; d="scan'208";a="230935405" Received: from amlin-019-225.igk.intel.com ([10.102.19.225]) by fmviesa006.fm.intel.com with ESMTP; 04 May 2026 07:24:57 -0700 From: Aleksandr Loktionov To: intel-wired-lan@lists.osuosl.org, anthony.l.nguyen@intel.com, aleksandr.loktionov@intel.com Cc: netdev@vger.kernel.org Subject: [PATCH iwl-next v2 3/5] ice: add correct handling of SMA/u.FL states Date: Mon, 4 May 2026 16:24:49 +0200 Message-ID: <20260504142451.4161845-4-aleksandr.loktionov@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260504142451.4161845-1-aleksandr.loktionov@intel.com> References: <20260504142451.4161845-1-aleksandr.loktionov@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The ICE_SMA2_UFL2_RX_DIS bit name is wrong: the bit is active high (setting it *enables* RX for u.FL2 / SMA2), not active low. Rename it to ICE_SMA2_UFL2_RX_EN and invert the use sites in ice_dpll.c so that enabling the u.FL2 pin clears the bit (as it used to do) and disabling sets it. Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control") Signed-off-by: Aleksandr Loktionov --- drivers/net/ethernet/intel/ice/ice_dpll.c | 6 +++--- drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c index 62f75701d..7e8bb63 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -672,7 +672,7 @@ ice_dpll_sw_pins_update(struct ice_pf *pf) p->active = false; p = &d->ufl[ICE_DPLL_PIN_SW_2_IDX]; - p->active = (data & ICE_SMA2_DIR_EN) && !(data & ICE_SMA2_UFL2_RX_DIS); + p->active = (data & ICE_SMA2_DIR_EN) && !(data & ICE_SMA2_UFL2_RX_EN); d->sma_data = data; return 0; @@ -1264,10 +1264,10 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv, case ICE_DPLL_PIN_SW_2_IDX: if (state == DPLL_PIN_STATE_SELECTABLE) { data |= ICE_SMA2_DIR_EN; - data &= ~ICE_SMA2_UFL2_RX_DIS; + data &= ~ICE_SMA2_UFL2_RX_EN; enable = true; } else if (state == DPLL_PIN_STATE_DISCONNECTED) { - data |= ICE_SMA2_UFL2_RX_DIS; + data |= ICE_SMA2_UFL2_RX_EN; enable = false; } else { goto unlock; diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index c1aa408..278d757 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -655,12 +655,12 @@ static inline u64 ice_get_base_incval(struct ice_hw *hw) /* SMA controller pin control */ #define ICE_SMA1_DIR_EN BIT(4) #define ICE_SMA1_TX_EN BIT(5) -#define ICE_SMA2_UFL2_RX_DIS BIT(3) +#define ICE_SMA2_UFL2_RX_EN BIT(3) #define ICE_SMA2_DIR_EN BIT(6) #define ICE_SMA2_TX_EN BIT(7) #define ICE_SMA1_MASK (ICE_SMA1_DIR_EN | ICE_SMA1_TX_EN) -#define ICE_SMA2_MASK (ICE_SMA2_UFL2_RX_DIS | ICE_SMA2_DIR_EN | \ +#define ICE_SMA2_MASK (ICE_SMA2_UFL2_RX_EN | ICE_SMA2_DIR_EN | \ ICE_SMA2_TX_EN) #define ICE_SMA2_INACTIVE_MASK (ICE_SMA2_DIR_EN | ICE_SMA2_TX_EN) #define ICE_ALL_SMA_MASK (ICE_SMA1_MASK | ICE_SMA2_MASK) -- 2.52.0