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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2] net: phy: dp83867: add MDI-X management Date: Wed, 6 May 2026 16:19:06 +0200 Message-ID: <20260506141918.13136-1-l.ellero@asem.it> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 06 May 2026 14:19:29.0477 (UTC) FILETIME=[59F17750:01DCDD63] X-Report-Abuse: Please forward a copy of this message, including all headers, to Feedback-ID: 1174574m:1174574aXfMg4B:1174574slHq65a5AS X-smtpcorp-track: qsu1muN0bPRH.fTs8PfxIGjpr.RsAtGwHbQq5 ethtool on this phy device always reports "MDI-X: Unknown" and doesn't support forcing it to on or off. This patch adds support for reading/forcing MDI-X mode from ethtool properly. Signed-off-by: Luca Ellero Reviewed-by: Andrew Lunn --- v2: - add net-next to patch subject (no code modifications) v1: https://lore.kernel.org/netdev/9414fa96-05e1-4d7e-adca-4ccf3b96853b@lunn.ch/T/#t drivers/net/phy/dp83867.c | 60 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 3fb2293f568f..88255e92b4cd 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -103,6 +103,10 @@ #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) #define DP83867_PHYCR_SGMII_EN BIT(11) #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) +#define DP83867_PHYCR_MDIX_MASK GENMASK(6, 5) +#define DP83867_PHYCR_MDIX_MDI (0x0 << 5) +#define DP83867_PHYCR_MDIX_MDIX (0x1 << 5) +#define DP83867_PHYCR_MDIX_AUTO (0x3 << 5) /* RGMIIDCTL bits */ #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf @@ -123,6 +127,10 @@ #define DP83867_PHYSTS_100 BIT(14) #define DP83867_PHYSTS_DUPLEX BIT(13) #define DP83867_PHYSTS_LINK BIT(10) +#define DP83867_PHYSTS_MDIX_CD BIT(9) +#define DP83867_PHYSTS_MDIX_AB BIT(8) +#define DP83867_PHYSTS_MDIX_MASK (DP83867_PHYSTS_MDIX_AB | \ + DP83867_PHYSTS_MDIX_CD) /* CFG2 bits */ #define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9)) @@ -391,6 +399,22 @@ static int dp83867_read_status(struct phy_device *phydev) else phydev->speed = SPEED_10; + if (!(status & DP83867_PHYSTS_LINK)) { + phydev->mdix = ETH_TP_MDI_INVALID; + } else { + switch (status & DP83867_PHYSTS_MDIX_MASK) { + case 0: + phydev->mdix = ETH_TP_MDI; + break; + case DP83867_PHYSTS_MDIX_MASK: + phydev->mdix = ETH_TP_MDI_X; + break; + default: + phydev->mdix = ETH_TP_MDI_INVALID; + break; + } + } + return 0; } @@ -714,6 +738,8 @@ static int dp83867_config_init(struct phy_device *phydev) struct dp83867_private *dp83867 = phydev->priv; int ret, val, bs; + phydev->mdix_ctrl = ETH_TP_MDI_AUTO; + /* Force speed optimization for the PHY even if it strapped */ ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN, DP83867_DOWNSHIFT_EN); @@ -873,6 +899,39 @@ static int dp83867_config_init(struct phy_device *phydev) return 0; } +static int dp83867_config_mdix(struct phy_device *phydev, u8 ctrl) +{ + int val; + + switch (ctrl) { + case ETH_TP_MDI: + val = DP83867_PHYCR_MDIX_MDI; + break; + case ETH_TP_MDI_X: + val = DP83867_PHYCR_MDIX_MDIX; + break; + case ETH_TP_MDI_AUTO: + val = DP83867_PHYCR_MDIX_AUTO; + break; + default: + return -EINVAL; + } + + return phy_modify(phydev, MII_DP83867_PHYCTRL, + DP83867_PHYCR_MDIX_MASK, val); +} + +static int dp83867_config_aneg(struct phy_device *phydev) +{ + int ret; + + ret = dp83867_config_mdix(phydev, phydev->mdix_ctrl); + if (ret) + return ret; + + return genphy_config_aneg(phydev); +} + static int dp83867_phy_reset(struct phy_device *phydev) { int err; @@ -1127,6 +1186,7 @@ static struct phy_driver dp83867_driver[] = { .probe = dp83867_probe, .config_init = dp83867_config_init, + .config_aneg = dp83867_config_aneg, .soft_reset = dp83867_phy_reset, .read_status = dp83867_read_status, -- 2.43.0