From: Conor Dooley <conor@kernel.org>
To: 李志 <lizhi2@eswincomputing.com>
Cc: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com,
kuba@kernel.org, pabeni@redhat.com, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com,
rmk+kernel@armlinux.org.uk, maxime.chevallier@bootlin.com,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org, ningyu@eswincomputing.com,
linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com,
pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com
Subject: Re: Re: [PATCH net v1 1/2] dt-bindings: ethernet: eswin: refine delay model and HSP register description
Date: Fri, 8 May 2026 15:55:40 +0100 [thread overview]
Message-ID: <20260508-detention-frisk-84cff00cb228@spud> (raw)
In-Reply-To: <22d09a07.7cfd.19e061cacea.Coremail.lizhi2@eswincomputing.com>
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On Fri, May 08, 2026 at 01:43:23PM +0800, 李志 wrote:
>
>
>
> > -----原始邮件-----
> > 发件人: "Conor Dooley" <conor@kernel.org>
> > 发送时间:2026-05-08 01:24:02 (星期五)
> > 收件人: lizhi2@eswincomputing.com
> > 抄送: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, maxime.chevallier@bootlin.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com
> > 主题: Re: [PATCH net v1 1/2] dt-bindings: ethernet: eswin: refine delay model and HSP register description
> >
> > On Thu, May 07, 2026 at 04:31:36PM +0800, lizhi2@eswincomputing.com wrote:
> > > From: Zhi Li <lizhi2@eswincomputing.com>
> > >
> > > Refine the EIC7700 Ethernet dt-binding based on observed hardware behavior
> > > and clarify the original delay model for eth0.
> > >
> > > The previous binding used an enum-based definition for
> > > rx-internal-delay-ps and tx-internal-delay-ps. Replace it with a
> > > range-based model using:
> > >
> > > - minimum: 0
> > > - maximum: 2540
> > > - multipleOf: 20
> > >
> > > This better reflects the actual hardware implementation, which
> > > supports 20ps granularity delay steps in the MAC RGMII interface.
> > >
> > > The tx/rx internal delay values are clarified as MAC-side programmable
> > > delay components applied on the RGMII clock/data path, representing
> > > the effective delay seen at the MAC interface.
> > >
> > > This does not change the intended hardware semantics, but aligns the
> > > binding with the actual hardware implementation.
> > >
> > > These properties are optional and only required when MAC-side fine
> > > tuning is needed; otherwise delay alignment is provided by PHY or
> > > board design.
> > >
> > > Depending on the selected RGMII timing mode, delay alignment may be
> > > provided by the PHY (e.g. rgmii-id) or by board/MAC-side configuration.
> > > When PHY or board design already provides the required delay, these
> > > MAC-side properties may be omitted. When MAC-side fine tuning is
> > > required, they should be provided to describe the internal RGMII
> > > timing adjustment.
> > >
> > > Additionally, extend the description of the HSP subsystem register
> > > layout used by the MAC glue logic. This includes explicit TXD and RXD
> > > delay control registers to ensure deterministic initialization and
> > > to override any residual configuration potentially left by bootloaders.
> > >
> > > Add reference to the EIC7700X SoC Technical Reference Manual,
> > > Chapter 10 ("High-Speed Interface"), Part 4 for background of the
> > > HSP CSR block:
> > > https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
> > >
> > > There are no in-tree users of this binding, so no ABI impact is
> > > expected.
> > >
> > > Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")
> > > Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
> > > ---
> >
> > While this is v1, it's really v8 and there should therefore be a
> > changelog that explains where my ack and the new compatible went.
> >
>
> Thanks for the review.
>
> Based on Jakub's feedback on the previous v7 series, I plan to split the
> changes into two separate series:
>
> - a smaller fix series intended for net,
> - and a separate eth1 feature series intended for net-next.
>
> After the split, the scope and target trees of the two series will differ
> from the original combined series, so I plan to restart the revision
> numbering from v1 for both series.
>
> The additional compatible string and the eth1-specific DT binding
> extensions will be moved into the separate feature series, and I will
> reflect this in the v2 cover letter.
>
> The DT binding changes in this fix series v1 are simply extracted from the
> previous v7 series as part of the split.
>
> Since the series has been restructured, I will drop the previous
> Acked-by tags.
>
> I will also document the reason for doing so and the impact of the split
> in the v2 cover letter.
This isn't what I am looking for. I just want/wanted an explanation for
why the new compatible has been removed from the patch.
>
> If you think the binding changes are still effectively unchanged and the
> previous Acked-by can still apply, I am happy to retain them or re-apply
> them as appropriate. Otherwise I will assume a fresh review is preferred.
If the removed compatible is the one for eth1, then
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
>
> Please let me know your preference.
>
> Thanks,
> Zhi
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next prev parent reply other threads:[~2026-05-08 14:55 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-07 8:30 [PATCH net v1 0/2] net: stmmac: eic7700: fix delay calculation and initialization ordering lizhi2
2026-05-07 8:31 ` [PATCH net v1 1/2] dt-bindings: ethernet: eswin: refine delay model and HSP register description lizhi2
2026-05-07 12:29 ` Andrew Lunn
2026-05-08 5:47 ` 李志
2026-05-07 17:24 ` Conor Dooley
2026-05-08 5:43 ` 李志
2026-05-08 14:55 ` Conor Dooley [this message]
2026-05-07 8:32 ` [PATCH net v1 2/2] net: stmmac: eic7700: fix delay step calculation and ensure safe register initialization lizhi2
2026-05-07 11:21 ` Maxime Chevallier
2026-05-08 6:25 ` 李志
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