From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C10DA3EDE6A for ; Tue, 12 May 2026 19:20:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778613644; cv=none; b=aBacMAERXfKq6uOx4rcJdybyH4Da1u1ODmUOmp2jPOTQewctdiGIDDAqc4/ePpg4pNATJaFyWQy//Lrj/ZcloT7IAGjuIKI1hd65WzOOESIXKYrspZMFz8ktzIS3FYFfokjIwlFrKsoSqrHE+YOHnakj8f3LFRie7Hbi1+J6Gmg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778613644; c=relaxed/simple; bh=NRVg9SrW7wmTvUbkSGKiMdp5aiUE/KRVZAijeUgUSrE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u3anT4O/aWYbzmCbkyzs5ubASXFaf5IkW4dTtexI4VyeGv36zWeOfkz5FZ0dAQ21djph+n0kYH5RVqhSMumvEzYHIeUkU35BgPucSIUE+bw6O7HZ+yFEtvRGo6wo9ult/QB6UxtKNwd9cjq3ZIa2P/cWvLl2gpUwqXoQvfydUR0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QSzwShUP; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QSzwShUP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1778613643; x=1810149643; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NRVg9SrW7wmTvUbkSGKiMdp5aiUE/KRVZAijeUgUSrE=; b=QSzwShUPfQJYNLL7RriUEmxwJRRqiC1yE1g8QY4BCswfqsIgWB+cQ70u AoAX/2kIMKEi09rfYrcY9u+OEpSuKS1YLkh0HfeAknTfyuxjAnlRE2s5P IpfiOyiM6G2jdVMJsUbWLtHry4nmT9JtS28EHRUNGWg3TPZ5L6TJxLg0w pAFrvwEX9jUtNQbSWRjcIyvkYrBldjUJ+xnV1slJYbGmY/Cfwo02CCb0m hc86P8DB9zGMLHmQjvHQrURQM1EBmpTr9ZNHwbmPkET7VviK15ymEE6zp 8Np/ltULbj5RoRDU8WzxVwKI7zM2icL2SAE4OKMCW/3/wRFlT2PvNvqXn w==; X-CSE-ConnectionGUID: SE678hRCQYOhZYCUfyaz1w== X-CSE-MsgGUID: Q5SOAlGSRzmU3xV4m4HNQA== X-IronPort-AV: E=McAfee;i="6800,10657,11784"; a="83406499" X-IronPort-AV: E=Sophos;i="6.23,231,1770624000"; d="scan'208";a="83406499" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2026 12:20:42 -0700 X-CSE-ConnectionGUID: ZpTqIGx/SxmK/UB35VGGGg== X-CSE-MsgGUID: LT783kByRv6HJr3jBQqd7A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,231,1770624000"; d="scan'208";a="237781644" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by orviesa008.jf.intel.com with ESMTP; 12 May 2026 12:20:37 -0700 From: Raag Jadav To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, netdev@vger.kernel.org Cc: simona.vetter@ffwll.ch, airlied@gmail.com, kuba@kernel.org, lijo.lazar@amd.com, Hawking.Zhang@amd.com, davem@davemloft.net, pabeni@redhat.com, edumazet@google.com, maarten@lankhorst.se, zachary.mckevitt@oss.qualcomm.com, rodrigo.vivi@intel.com, riana.tauro@intel.com, michal.wajdeczko@intel.com, matthew.d.roper@intel.com, umesh.nerlige.ramappa@intel.com, mallesh.koujalagi@intel.com, anoop.c.vijay@intel.com, aravind.iddamsetty@linux.intel.com, Raag Jadav Subject: [PATCH v2 9/9] drm/xe/xe_ras: Control xe drm_ras registration with a flag Date: Wed, 13 May 2026 00:46:10 +0530 Message-ID: <20260512191610.1817578-10-raag.jadav@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260512191610.1817578-1-raag.jadav@intel.com> References: <20260512191610.1817578-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Riana Tauro Add a flag to control xe drm_ras registration. Enable this flag for PVC and CRI to support exposing RAS error counters via netlink. Signed-off-by: Riana Tauro Reviewed-by: Raag Jadav info.is_dgfx = desc->is_dgfx; xe->info.has_cached_pt = desc->has_cached_pt; + xe->info.has_drm_ras = desc->has_drm_ras; xe->info.has_fan_control = desc->has_fan_control; /* runtime fusing may force flat_ccs to disabled later */ xe->info.has_flat_ccs = desc->has_flat_ccs; diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h index 5b85e2c24b7b..24d4a3d00517 100644 --- a/drivers/gpu/drm/xe/xe_pci_types.h +++ b/drivers/gpu/drm/xe/xe_pci_types.h @@ -40,6 +40,7 @@ struct xe_device_desc { u8 has_cached_pt:1; u8 has_display:1; + u8 has_drm_ras:1; u8 has_fan_control:1; u8 has_flat_ccs:1; u8 has_gsc_nvm:1; diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c index 57ee0ed0d46c..7464057839ec 100644 --- a/drivers/gpu/drm/xe/xe_ras.c +++ b/drivers/gpu/drm/xe/xe_ras.c @@ -233,7 +233,7 @@ void xe_ras_init(struct xe_device *xe) { int ret; - if (xe->info.platform != XE_PVC) + if (!xe->info.has_drm_ras) return; ret = xe_drm_ras_init(xe); -- 2.43.0