From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E6E336F8EF for ; Tue, 12 May 2026 19:20:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778613640; cv=none; b=KCG061JsWuAU7Ut5okXYmYhCMkCTjxPCIMKK/LMWRhq1SVXgLLnaQ28Ggjc6Ejn6ctVlRSW8Ckzr50d3vaRbz8TkQHiI0O+yDGdHrPRus8I54aiPP7+RedSfT9XU90VjyMU233lDv1R89yV4uSZ4ynsgk55FzXtfynyRGEf0h58= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778613640; c=relaxed/simple; bh=rlohRXGNCTcR+Ehy5LuCXsrgQ99ZDmhXhXa5dYsoOXc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AAf5uSz8x2oXFonojmB1AtGDZnQVUmxDkqH5gAvPiViCPu7ECs/qZ+hxFXhW2p311rcuUfIk+m87PBoncuOaOFxn1SPD0Ww9pUzSKTRzAHvcxcK22nkY4GANtblWiUixloxd2/XqskYLulgfk8N8MBr9d04a2RXcUg2x234xt5A= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EO/HyWHp; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EO/HyWHp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1778613639; x=1810149639; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rlohRXGNCTcR+Ehy5LuCXsrgQ99ZDmhXhXa5dYsoOXc=; b=EO/HyWHpQoERIiPoi2ybwCOhWNcoMP3A98xBO8mq96V7BogV0O7PizyQ yguQ8ke7Cr5ZTaaUTkf8nRYzyhXI5NEnlKIy6wRtQmTtAh+XorO25Bq+t 3nhk/ms3TQ5xrudq4wnSskLAzbWqPaC2R1r9dRM5Ko30bKbLUENbQzg6t bw009IW9IF+UTIDLpsskexJ4ud+QONvs/BZ39Qq6+po1+57OK8PWKw8Xt Vqpu3Dy2N66NgzK5eyHjviJrOnoAgaIjLRszdTpxt7+MQPEK/1NCJQF34 k9n/+ji0Ngovto4QvFDoH1cftAsxb7x3MV2Sbd1zGp/BULvk+4zMcEJZB g==; X-CSE-ConnectionGUID: AakXVaArRuy2BtMIvUw8vw== X-CSE-MsgGUID: XEDdE6bVTwaxKMcDpcrq4g== X-IronPort-AV: E=McAfee;i="6800,10657,11784"; a="83406478" X-IronPort-AV: E=Sophos;i="6.23,231,1770624000"; d="scan'208";a="83406478" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2026 12:20:36 -0700 X-CSE-ConnectionGUID: k6AqtWQQQSq68DYn34r+5A== X-CSE-MsgGUID: p5ucdyk8Q2WQMIK4zFHJZg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,231,1770624000"; d="scan'208";a="237781606" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by orviesa008.jf.intel.com with ESMTP; 12 May 2026 12:20:31 -0700 From: Raag Jadav To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, netdev@vger.kernel.org Cc: simona.vetter@ffwll.ch, airlied@gmail.com, kuba@kernel.org, lijo.lazar@amd.com, Hawking.Zhang@amd.com, davem@davemloft.net, pabeni@redhat.com, edumazet@google.com, maarten@lankhorst.se, zachary.mckevitt@oss.qualcomm.com, rodrigo.vivi@intel.com, riana.tauro@intel.com, michal.wajdeczko@intel.com, matthew.d.roper@intel.com, umesh.nerlige.ramappa@intel.com, mallesh.koujalagi@intel.com, anoop.c.vijay@intel.com, aravind.iddamsetty@linux.intel.com, Raag Jadav Subject: [PATCH v2 8/9] drm/xe/xe_ras: Move xe drm_ras registration Date: Wed, 13 May 2026 00:46:09 +0530 Message-ID: <20260512191610.1817578-9-raag.jadav@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260512191610.1817578-1-raag.jadav@intel.com> References: <20260512191610.1817578-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Riana Tauro gove xe drm_ras registration to RAS initialization flow and keep gardware error initialization for processing errors reported via irq. Also reorder soc remapper and system controller initialization to early probe as ras init is dependent on both. Cc: Anoop Vijay Cc: Umesh Nerlige Ramappa Signed-off-by: Riana Tauro --- drivers/gpu/drm/xe/xe_device.c | 19 +++++++++++-------- drivers/gpu/drm/xe/xe_hw_error.c | 13 ------------- drivers/gpu/drm/xe/xe_ras.c | 20 ++++++++++++++++++++ drivers/gpu/drm/xe/xe_ras.h | 1 + 4 files changed, 32 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 65f107ba1410..402504971e3d 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -63,6 +63,7 @@ #include "xe_psmi.h" #include "xe_pxp.h" #include "xe_query.h" +#include "xe_ras.h" #include "xe_shrinker.h" #include "xe_soc_remapper.h" #include "xe_survivability_mode.h" @@ -964,6 +965,16 @@ int xe_device_probe(struct xe_device *xe) if (err) return err; + err = xe_soc_remapper_init(xe); + if (err) + return err; + + err = xe_sysctrl_init(xe); + if (err) + return err; + + xe_ras_init(xe); + /* * Now that GT is initialized (TTM in particular), * we can try to init display, and inherit the initial fb. @@ -1004,10 +1015,6 @@ int xe_device_probe(struct xe_device *xe) xe_nvm_init(xe); - err = xe_soc_remapper_init(xe); - if (err) - return err; - err = xe_heci_gsc_init(xe); if (err) return err; @@ -1046,10 +1053,6 @@ int xe_device_probe(struct xe_device *xe) if (err) goto err_unregister_display; - err = xe_sysctrl_init(xe); - if (err) - goto err_unregister_display; - err = xe_device_sysfs_init(xe); if (err) goto err_unregister_display; diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c index 5135e8e4093f..e0ae6fee2c0e 100644 --- a/drivers/gpu/drm/xe/xe_hw_error.c +++ b/drivers/gpu/drm/xe/xe_hw_error.c @@ -516,14 +516,6 @@ void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl) } } -static int hw_error_info_init(struct xe_device *xe) -{ - if (xe->info.platform != XE_PVC) - return 0; - - return xe_drm_ras_init(xe); -} - /* * Process hardware errors during boot */ @@ -550,16 +542,11 @@ static void process_hw_errors(struct xe_device *xe) void xe_hw_error_init(struct xe_device *xe) { struct xe_tile *tile = xe_device_get_root_tile(xe); - int ret; if (!IS_DGFX(xe) || IS_SRIOV_VF(xe)) return; INIT_WORK(&tile->csc_hw_error_work, csc_hw_error_work); - ret = hw_error_info_init(xe); - if (ret) - drm_err(&xe->drm, "Failed to initialize XE DRM RAS (%pe)\n", ERR_PTR(ret)); - process_hw_errors(xe); } diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c index 4548e5cb08b9..57ee0ed0d46c 100644 --- a/drivers/gpu/drm/xe/xe_ras.c +++ b/drivers/gpu/drm/xe/xe_ras.c @@ -4,6 +4,7 @@ */ #include "xe_device.h" +#include "xe_drm_ras.h" #include "xe_pm.h" #include "xe_printk.h" #include "xe_ras.h" @@ -221,3 +222,22 @@ int xe_ras_set_threshold(struct xe_device *xe, u32 severity, u32 component, u32 comp_to_str(counter.common.component), sev_to_str(counter.common.severity)); return 0; } + +/** + * xe_ras_init - Initialize Xe RAS + * @xe: xe device instance + * + * Initialize Xe RAS + */ +void xe_ras_init(struct xe_device *xe) +{ + int ret; + + if (xe->info.platform != XE_PVC) + return; + + ret = xe_drm_ras_init(xe); + if (ret) + drm_err(&xe->drm, "Failed to initialize xe_drm_ras %d\n", ret); +} + diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h index d1f71b1de723..b6bc50863fa6 100644 --- a/drivers/gpu/drm/xe/xe_ras.h +++ b/drivers/gpu/drm/xe/xe_ras.h @@ -11,6 +11,7 @@ struct xe_device; struct xe_sysctrl_event_response; +void xe_ras_init(struct xe_device *xe); void xe_ras_counter_threshold_crossed(struct xe_device *xe, struct xe_sysctrl_event_response *response); int xe_ras_get_threshold(struct xe_device *xe, u32 severity, u32 component, u32 *threshold); -- 2.43.0