Re: [PATCH] can: m_can: Implement workaround for errata i2278 and i2279

[Marc Kleine-Budde <mkl@pengutronix.de>]

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On 14.05.2026 12:25:11, Anurag Dutta wrote:
> Message transmit order is not guaranteed when dedicated TX buffers
> configured with the same Message ID are submitted simultaneously via
> TXBAR write. This is described in J7 errata i2278 and i2279.
>
> As a workaround, introduce m_can_tx_peripheral_submit() to submit
> buffers one at a time using ffs() to find the next pending buffer.
> The TX complete interrupt(IR_TC) triggers submission of the next
> buffer, ensuring strict FIFO ordering.
>
> Link: https://www.ti.com/lit/pdf/sprz530

This errata is for the "J721S2/TDA4VE/TDA4AL/TDA4VL/AM68A Processor
Silicon Revision 1.0". The code path you modify is only active for the
is_peripheral case.

is_peripheral is only set for the tcan4x5x SPI CAN controller, and not
set for memory mapped M_CAN cores as found on the above mentioned TI
processor:

| $ git grep peripheral\ = drivers/net/can/m_can
| drivers/net/can/m_can/m_can_platform.c:149:      mcan_class->is_peripheral = false;
| drivers/net/can/m_can/tcan4x5x-core.c:460:       mcan_class->is_peripheral = true;

The latest Bosch m_can documentation doesn't mention this problem,
neither the TCAN4550 docs. Can this be an integration problem of the SoC
on TI's side?

regards,
Marc

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