From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0A973E2AD3 for ; Fri, 15 May 2026 19:04:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778871868; cv=none; b=od2nBymZwTZ7aUBVqMPG/rdHtRUDWYXx2/jldBhM56d3hx9VSN/aq2dub6eeaCAXEk6GxxJLNYb8gBzDuZGHrCwUTKlUz/9jwxVWRqLfGn9N5KTSMKBabNjb7h01u9vr3rKMuSgz0nxaIfLsbPmVGeE/O6JS6sgqXGww8eNy1GM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778871868; c=relaxed/simple; bh=G7MmTf1h+5LioLTjjvjCKQN7jxTwWDeJLS/XSkZaGHM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=S86QKjDjn9mQw7nbmwVKsQmVOfHzwZA+3lX6TmxGvdkhlPln7MV0hTpipOhJ8Q5BM70GU9rER/GCbPg8CY2srqPgaCKdF6ASPfKafwHiLxuigIM5iOoCaFYYTFPkU8tRb7gFKWqzRFgcUDEM3YjjIu1hJj9x5tRkViGkzBI5XTU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MvkjCTnq; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MvkjCTnq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1778871867; x=1810407867; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G7MmTf1h+5LioLTjjvjCKQN7jxTwWDeJLS/XSkZaGHM=; b=MvkjCTnqQbiwKoz89WwkplQpqP77hIQEDyBtI0zMguynNft2sspo4lly 3OgjPqUKK6E45CcgTlfG/RIBtBuzNwJ4L9+GgvoBe7Mk3AQ9fHLMks49R IoI0GYFszpMu9XQJ+rTarmDt1TLjMu/jmKFL/ChbkTgIXxL333AJkWKwt Wwr9Sft5bX+lgxuICSjgsqg7aTiJPHp/b6YA1e9FjbUTIxWnWtitQHvlK bllLFWBzvwv91fMHA7bGlJKuWYSh0oVlI0TxyW3lZWxwWUXF7KRNjfiki sa5hCrboD7FEDoiiOdccavoTOyVifFidgh/Hfolz8PjuSHceYdQskcm+5 g==; X-CSE-ConnectionGUID: 76Kbae2tQxyjW6NvjeSL9g== X-CSE-MsgGUID: /KiGfXZJRRy7f0h+TSV27Q== X-IronPort-AV: E=McAfee;i="6800,10657,11787"; a="79725709" X-IronPort-AV: E=Sophos;i="6.23,236,1770624000"; d="scan'208";a="79725709" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2026 12:04:26 -0700 X-CSE-ConnectionGUID: Su3c0a8XREq15JaTI2zyKg== X-CSE-MsgGUID: 2ZgFqH7BRuajeK2M+Fr8qQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,236,1770624000"; d="scan'208";a="238895636" Received: from amlin-019-225.igk.intel.com ([10.102.19.225]) by orviesa009.jf.intel.com with ESMTP; 15 May 2026 12:04:25 -0700 From: Aleksandr Loktionov To: intel-wired-lan@lists.osuosl.org, anthony.l.nguyen@intel.com, aleksandr.loktionov@intel.com Cc: netdev@vger.kernel.org, Simon Horman Subject: [PATCH iwl-net v5 4/4] ixgbe: fix integer overflow and wrong bit position in ixgbe_validate_rtr() Date: Fri, 15 May 2026 21:04:17 +0200 Message-ID: <20260515090000.5112345-5-aleksandr.loktionov@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260515090000.5112345-1-aleksandr.loktionov@intel.com> References: <20260515090000.5112345-1-aleksandr.loktionov@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Two bugs in the same loop in ixgbe_validate_rtr(): 1. The 3-bit traffic-class field was extracted by shifting a u32 and assigning the result directly to a u8. For user priority 0 this is harmless; for UP[5..7] the shift leaves bits [15..21] in the u32 which are then silently truncated when stored in u8. Mask with IXGBE_RTRUP2TC_UP_MASK before the assignment so only the intended 3 bits are kept. 2. When clearing an out-of-bounds entry the mask was always shifted by the fixed constant IXGBE_RTRUP2TC_UP_SHIFT (== 3), regardless of which loop iteration was being processed. This means only UP1 (bit position 3) was ever cleared; UP0,2..7 (positions 0, 6, 9, ..., 21) were left unreset, so invalid TC mappings persisted in hardware and could mis-steer received packets to the wrong traffic class. Use i * IXGBE_RTRUP2TC_UP_SHIFT to target the correct 3-bit field for each iteration. Swap the operand order in the mask expression to place the constant on the right per kernel coding style (noted by David Laight). Fixes: 8b1c0b24d9af ("ixgbe: configure minimal packet buffers to support TC") Cc: stable@vger.kernel.org Reviewed-by: Simon Horman Signed-off-by: Aleksandr Loktionov --- v2 -> v3: - Correct Fixes: tag to 8b1c0b24d9af ("ixgbe: configure minimal packet buffers to support TC") -- the previously used e7589eab9291 predates the buggy code path (Simon Horman); add Reviewed-by: Simon Horman. v1 -> v2: - Add Fixes: tag; reroute to iwl-net (wrong bit positions cause packet mis-steering); swap to (reg >> ...) & MASK operand order per David Laight. drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c index 210c7b9..c9e4f12 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c @@ -9772,11 +9772,12 @@ static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) rsave = reg; for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { - u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); + u8 up2tc = (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)) & + IXGBE_RTRUP2TC_UP_MASK; /* If up2tc is out of bounds default to zero */ if (up2tc > tc) - reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); + reg &= ~(IXGBE_RTRUP2TC_UP_MASK << (i * IXGBE_RTRUP2TC_UP_SHIFT)); } if (reg != rsave) -- 2.52.0