From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 785B83E1687 for ; Fri, 15 May 2026 18:24:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778869473; cv=none; b=oYJceA34RmeB+5EyQYDi1kJjGzytDzZCEV9xdhspftEIt+ca4tMgzJSZ7fNyYp4O/YHEg8GrR0CoyqscAKQQvhLXOXZqrBEJRNOm8OOrkNZGE2E5C3jP1K5oHbSBQ1KkbhZNtsVkAfEuiHKnQy1vHypxfRBSt7UrGSTcerkcExk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778869473; c=relaxed/simple; bh=N1ZSOstuCjCWm57XWMqQLhOS2X8yUGcEM81+6E1R2yE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=huprMs5OvZt91g+jAVGxJHG7CLLpzfS/KIoQ3tggVcD8fuiSTRy9aQv7ED0PglU/o395RE8ySCRRRgNbevksxM4U0/YIIaCqtX5q4RHUK+020htwThD8HfHyjaCAetAVaD+KoDFsu/UomANkMmZ5wHKkXfCevl4dCRHnlSA0IUM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Ek7OQIx9; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Ek7OQIx9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1778869472; x=1810405472; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=N1ZSOstuCjCWm57XWMqQLhOS2X8yUGcEM81+6E1R2yE=; b=Ek7OQIx9VyJhIJ29Pq20jD5blENHS1++MMneekansl2+3+OIQUbp/ecm ynHpkS2oO1uxhHGZCEOcbu1ag2j+31HzuAEYvAmMYgu3SvofSABx0f2rs RtVbU5QIvk2JG9xAm+kbI1ymdpLxMdf1FHU6bn69o2uBfLsZrW8iKTZv9 jQ4IA65aqwgBLuuZujMp8egt9RW3u9c28vwin2FPne5I3VOOP4K6MlRnc 9u0aev6nKjjQiQNuRozTsIb0OpsJ5nk8zj7cRxeMxGMSbt9AP06ziEFk1 lcBhF0nsAXSIZJaIsg2WBTEnCfltsmVRshTOFNRczrnuv0JE3gOVUFYCc w==; X-CSE-ConnectionGUID: 2ptR6+zHQjSHeHzy+9FMzA== X-CSE-MsgGUID: KPPsn4cMT3WqbQ0i0S95Ag== X-IronPort-AV: E=McAfee;i="6800,10657,11787"; a="83701194" X-IronPort-AV: E=Sophos;i="6.23,236,1770624000"; d="scan'208";a="83701194" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2026 11:24:28 -0700 X-CSE-ConnectionGUID: QDSA4cvsQ6Cd2Cj7kHfthQ== X-CSE-MsgGUID: jc+BI0qZTkGlzZGRvxYvPw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,236,1770624000"; d="scan'208";a="238647464" Received: from anguy11-upstream.jf.intel.com ([10.166.9.133]) by orviesa008.jf.intel.com with ESMTP; 15 May 2026 11:24:27 -0700 From: Tony Nguyen To: davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com, edumazet@google.com, andrew+netdev@lunn.ch, netdev@vger.kernel.org Cc: Vitaly Lifshits , anthony.l.nguyen@intel.com, richardcochran@gmail.com, jacob.e.keller@intel.com, horms@kernel.org, Avigail Dahan Subject: [PATCH net 10/10] e1000e: correct TIMINCA on ADP/TGP systems with wrong XTAL frequency Date: Fri, 15 May 2026 11:24:17 -0700 Message-ID: <20260515182419.1597859-11-anthony.l.nguyen@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260515182419.1597859-1-anthony.l.nguyen@intel.com> References: <20260515182419.1597859-1-anthony.l.nguyen@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Vitaly Lifshits On some Tiger Lake (TGP) and Alder Lake (ADP) platforms, the hardware XTAL clock is incorrectly interpreted as 24 MHz instead of the actual 38.4 MHz. This causes the PHC to run significantly faster than system time, breaking PTP synchronization. To mitigate this at runtime, measure PHC vs system time over ~1 ms using cross-timestamps. If the PHC increment differs from system time beyond the expected tolerance (currently >100 uSecs), reprogram TIMINCA for the 38.4 MHz profile and reinitialize the timecounter. Tested on an affected system using phc_ctl: Without fix: sudo phc_ctl enp0s31f6 set 0.0 wait 10 get clock time: 16.000541250 (expected ~10s) With fix: sudo phc_ctl enp0s31f6 set 0.0 wait 10 get clock time: 9.984407212 (expected ~10s) Fixes: fb776f5d57ee ("e1000e: Add support for Tiger Lake") Signed-off-by: Vitaly Lifshits Co-developed-by: Dima Ruinskiy Signed-off-by: Dima Ruinskiy Tested-by: Avigail Dahan Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/e1000e/netdev.c | 78 ++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c index 7ce0cc8ab8f4..db2080541f19 100644 --- a/drivers/net/ethernet/intel/e1000e/netdev.c +++ b/drivers/net/ethernet/intel/e1000e/netdev.c @@ -3902,6 +3902,81 @@ static void e1000_flush_desc_rings(struct e1000_adapter *adapter) e1000_flush_rx_ring(adapter); } +/** + * e1000e_xtal_tgp_workaround - Adjust XTAL clock based on PHC and system + * clock delta. + * @adapter: Pointer to the private adapter structure + * + * Measures the time difference between the PHC (Precision Hardware Clock) + * and the system clock over a 1 millisecond interval. If the delta + * exceeds 100 microseconds, reconfigure the XTAL clock to 38.4 MHz. + */ +static void e1000e_xtal_tgp_workaround(struct e1000_adapter *adapter) +{ + s64 phc_delta, sys_delta, sys_start_ns, sys_end_ns, delta_ns; + struct ptp_system_timestamp sys_start = {}, sys_end = {}; + struct ptp_clock_info *info = &adapter->ptp_clock_info; + struct timespec64 phc_start, phc_end; + struct e1000_hw *hw = &adapter->hw; + struct netlink_ext_ack extack = {}; + unsigned long flags; + u32 timinca; + s32 ret_val; + + /* Capture start */ + if (info->gettimex64(info, &phc_start, &sys_start)) { + e_dbg("PHC gettimex(start) failed\n"); + return; + } + + /* Small interval to measure increment */ + usleep_range(1000, 1100); + + /* Capture end */ + if (info->gettimex64(info, &phc_end, &sys_end)) { + e_dbg("PHC gettimex(end) failed\n"); + return; + } + + /* Compute deltas */ + phc_delta = timespec64_to_ns(&phc_end) - + timespec64_to_ns(&phc_start); + + sys_start_ns = (timespec64_to_ns(&sys_start.pre_ts) + + timespec64_to_ns(&sys_start.post_ts)) >> 1; + + sys_end_ns = (timespec64_to_ns(&sys_end.pre_ts) + + timespec64_to_ns(&sys_end.post_ts)) >> 1; + + sys_delta = sys_end_ns - sys_start_ns; + + delta_ns = phc_delta - sys_delta; + if (delta_ns > 100000) { + e_dbg("Corrected PHC frequency: TIMINCA set for 38.4 MHz\n"); + /* Program TIMINCA for 38.4 MHz */ + spin_lock_irqsave(&adapter->systim_lock, flags); + adapter->cc.shift = INCVALUE_SHIFT_38400KHZ; + timinca = (INCPERIOD_38400KHZ << + E1000_TIMINCA_INCPERIOD_SHIFT) | + (((INCVALUE_38400KHZ << + adapter->cc.shift) & + E1000_TIMINCA_INCVALUE_MASK)); + ew32(TIMINCA, timinca); + + /* reset the systim ns time counter */ + timecounter_init(&adapter->tc, &adapter->cc, + ktime_get_real_ns()); + spin_unlock_irqrestore(&adapter->systim_lock, flags); + + /* restore the previous hwtstamp configuration settings */ + ret_val = e1000e_config_hwtstamp(adapter, + &adapter->hwtstamp_config, + &extack); + if (ret_val && extack._msg) + e_err("%s\n", extack._msg); + } +} + /** * e1000e_systim_reset - reset the timesync registers after a hardware reset * @adapter: board private structure @@ -3953,6 +4028,9 @@ static void e1000e_systim_reset(struct e1000_adapter *adapter) if (extack._msg) e_err("%s\n", extack._msg); } + + if (hw->mac.type == e1000_pch_adp || hw->mac.type == e1000_pch_tgp) + e1000e_xtal_tgp_workaround(adapter); } /** -- 2.47.1