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Wed, 20 May 2026 12:21:00 -0700 (PDT) From: Ali Rouhi X-Google-Original-From: Ali Rouhi To: jiri@resnulli.us Cc: vadim.fedorenko@linux.dev, arkadiusz.kubalewski@intel.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, cjubran@nvidia.com, Oleg.Zadorozhnyi@devoxsoftware.com, devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Ali Rouhi Subject: [PATCH v2 net-next 2/3] dt-bindings: dpll: add SiTime SiT9531x clock generator Date: Wed, 20 May 2026 12:19:42 -0700 Message-Id: <20260520191943.73938-3-arouhi@sitime.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20260520191943.73938-1-arouhi@sitime.com> References: <20260520191943.73938-1-arouhi@sitime.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add device tree binding documentation for the SiTime SiT95316 and SiT95317 DPLL clock generators. Co-developed-by: Oleg Zadorozhnyi Signed-off-by: Oleg Zadorozhnyi Signed-off-by: Ali Rouhi --- .../bindings/dpll/sitime,sit9531x.yaml | 145 ++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/dpll/sitime,sit9531x.yaml diff --git a/Documentation/devicetree/bindings/dpll/sitime,sit9531x.yaml b/Documentation/devicetree/bindings/dpll/sitime,sit9531x.yaml new file mode 100644 index 000000000000..ac88f2f0b2ae --- /dev/null +++ b/Documentation/devicetree/bindings/dpll/sitime,sit9531x.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dpll/sitime,sit9531x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiTime SiT9531x DPLL Clock Generator + +maintainers: + - Ali Rouhi + +description: | + SiTime SiT95316 and SiT95317 are I2C-controlled programmable clock + generators with integrated DPLL for synchronization applications. Both + variants contain four PLLs with automatic/manual reference selection, + DCO frequency adjustment, and phase offset measurement via an on-chip + TDC (Time-to-Digital Converter). + + SiT95317 provides 4 inputs and 8 outputs; SiT95316 provides + 4 inputs and 12 outputs. + +properties: + compatible: + enum: + - sitime,sit95316 + - sitime,sit95317 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: + External crystal/oscillator feeding the chip's XIN/XO_CLK input. + The chip's PLL Fvco is computed relative to this reference, so the + driver requires a non-zero rate at probe time. + + clock-names: + items: + - const: xtal + + reset-gpios: + maxItems: 1 + description: + GPIO connected to the chip's active-low reset pin (RESETB). + + interrupts: + maxItems: 1 + description: + Interrupt from the chip's active-low INTRB output. Asserted when + the device detects a status change such as lock acquisition or loss. + +required: + - compatible + - reg + - clocks + - clock-names + +allOf: + - $ref: /schemas/dpll/dpll-device.yaml# + +unevaluatedProperties: false + +examples: + - | + xo: xo { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + dpll@68 { + compatible = "sitime,sit95317"; + reg = <0x68>; + clocks = <&xo>; + clock-names = "xtal"; + }; + }; + + - | + #include + #include + + xo2: xo2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + dpll@68 { + compatible = "sitime,sit95316"; + reg = <0x68>; + clocks = <&xo2>; + clock-names = "xtal"; + reset-gpios = <&gpio 78 GPIO_ACTIVE_LOW>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + dpll-types = "eec", "eec", "eec", "eec"; + + input-pins { + #address-cells = <1>; + #size-cells = <0>; + + pin@0 { + reg = <0>; + label = "clkin0"; + connection-type = "ext"; + supported-frequencies-hz = /bits/ 64 <10000000>; + }; + + pin@1 { + reg = <1>; + label = "clkin1"; + connection-type = "synce"; + supported-frequencies-hz = /bits/ 64 <156250000>; + }; + }; + + output-pins { + #address-cells = <1>; + #size-cells = <0>; + + pin@0 { + reg = <0>; + label = "clkout0"; + esync-control; + supported-frequencies-hz = /bits/ 64 <156250000>; + }; + + pin@1 { + reg = <1>; + label = "clkout1"; + supported-frequencies-hz = /bits/ 64 <25000000>; + }; + }; + }; + }; +... -- 2.43.0