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Thu, 21 May 2026 00:24:54 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Jonathan Corbet , Shuah Khan , Jiri Pirko , Simon Horman , "Saeed Mahameed" , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Borislav Petkov (AMD)" , Andrew Morton , Randy Dunlap , Thomas Gleixner , Petr Mladek , "Peter Zijlstra (Intel)" , "Tejun Heo" , Vlastimil Babka , Feng Tang , Christian Brauner , "Dave Hansen" , Dapeng Mi , Kees Cook , Marco Elver , Li RongQing , Eric Biggers , "Paul E. McKenney" , , , , , Gal Pressman , Dragos Tatulea , Jiri Pirko , Shay Drori , Moshe Shemesh Subject: [PATCH net-next 1/3] net/mlx5: Clear FW reset-in-progress bit before reload Date: Thu, 21 May 2026 10:24:32 +0300 Message-ID: <20260521072434.362624-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260521072434.362624-1-tariqt@nvidia.com> References: <20260521072434.362624-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E5F:EE_|DS7PR12MB6261:EE_ X-MS-Office365-Filtering-Correlation-Id: 431180ed-9e73-4cae-68e4-08deb70a1d45 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|7416014|82310400026|22082099003|56012099003|18002099003|11063799006; X-Microsoft-Antispam-Message-Info: rFkd2NAdPHy0LxWGNX1MI7583EqqCqkM3wZ3/rGeKxArh0l6YsXyQNpNNDN3SzobLIWQPlH099fetIhEix8GOUknjv7jd2UF6HxU3KmhmR1l0sZvVIZYnddpBXQYDzCn+9UINe96c1znqxMMWw92MNP8p/QwLzmzpXFhRlyHG6rWImfJW41XtsOo3WC1qp9U9i02MbipVansMed1EI8NwMo4v3qQxd9YXhyqCWdo0dw0ExsOQ/Y8pektmw2RI2R1sPr1sEnX1TPtXw7G39NUD/FnDw83Mrke3YL8USErJQANnQ1ViTtg+gNxtgm8I7x+o2PNA6W6oyNj84CPMOxURGYx/d49PJ/mXDxzfownrdhl4v+BG7N5NAO7fbPopyOAjpCWxnECjNpfxcgfIXfPIjqK9vHhIbZbyYGRg2gSetYKoabQcupPUoCcoH9PIVSw4MQXxsmyZwkHKpAIabwwaJLmXJjFXCiOpOAPTUBCNCENsqN1XyaGTJrPyY+AR8OA/6/vrvT98o8Gh+03blhBdgJkZwtTOX6Ne6LroVw2Ll5qs0VAuucYDzynV4L7k1/nWS3AKtQJUd+HItR2w+No4e8BnwaG10XJ1d8+VD1mgNARFtmfsU3FmVCVHeJFO/53Ar7QvSh5pRdFR+bu3CM+YRZc1NnLIRrMyPCeIIbbnBZ2SVeoafFl8kvaz6rsG+PnUfZru0VFYyk8OXmRISd/SO+EPpCBA/9MPtO37LacjpM= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(376014)(7416014)(82310400026)(22082099003)(56012099003)(18002099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: odMayCZjGkBeqF19hxKslJhC1Fk0h8Mu0UA91FzGjBd4qbO45QEibWx0pNtA754IK5jomoWsRxKothuuJvIR2NqAH3z3wi0iEm4Y42IG1uayAuSMl2qtlkTBAIidlel1kndG4RLtaMKlxvcJOprBpcrP3hLifV2NVCaaJvhK9RXiHnM5ghkR2oahd0foimct3f3xUIJ0asBVuJDE4AqaO9JlMO4KTQWWbssL9sjfiTRGw4Uuf4XZC6jHHOoGt3eiGvZub7icjxxAYC2G8SFYYrwcso9o7gwsw2PFNlLRUGnVgGVsveTwgU1WBaeSGpyparJhaw8yk38S8CuCv8Rg/A8HlqznbvU7TN2vc2dAB6Q41JhIMI04qSHXq2jySANl9yFIW9/iwsYzRwQ8PM4WuaaNm1idz9AP3aTb/SRjFOuORT6NsnViX18mJsVZtGNw X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 07:25:20.1162 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 431180ed-9e73-4cae-68e4-08deb70a1d45 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E5F.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6261 From: Mark Bloch mlx5 sets MLX5_FW_RESET_FLAGS_RESET_IN_PROGRESS when acknowledging a sync reset request. This bit blocks devlink reload and other devlink operations while the firmware reset is running, but it was kept set until after the driver reload finished. Clear the reset-in-progress bit once the reset unload flow is done and PCI access is back, before reloading the device. For a reset initiated through devlink, clear it before completing the reload waiter. For a reset reported through an asynchronous firmware event, keep the unload flow outside devl_lock, then take devl_lock before clearing the bit and reloading through the devl-locked load helper. Signed-off-by: Mark Bloch Reviewed-by: Shay Drori Reviewed-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/fw_reset.c | 28 +++++++++++-------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c index 07440c58713a..7283e5b49eed 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c @@ -238,24 +238,30 @@ static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev) { struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset; struct devlink *devlink = priv_to_devlink(dev); + int err; /* if this is the driver that initiated the fw reset, devlink completed the reload */ if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) { + clear_bit(MLX5_FW_RESET_FLAGS_RESET_IN_PROGRESS, + &fw_reset->reset_flags); complete(&fw_reset->done); - } else { - mlx5_sync_reset_unload_flow(dev, false); - if (mlx5_health_wait_pci_up(dev)) - mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n"); - else - mlx5_load_one(dev, true); - devl_lock(devlink); - devlink_remote_reload_actions_performed(devlink, 0, - BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | - BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE)); - devl_unlock(devlink); + return; } + mlx5_sync_reset_unload_flow(dev, false); + err = mlx5_health_wait_pci_up(dev); + + devl_lock(devlink); clear_bit(MLX5_FW_RESET_FLAGS_RESET_IN_PROGRESS, &fw_reset->reset_flags); + if (err) + mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n"); + else + mlx5_load_one_devl_locked(dev, true); + + devlink_remote_reload_actions_performed(devlink, 0, + BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | + BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE)); + devl_unlock(devlink); } static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev) -- 2.44.0