From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2D003CB8F0 for ; Tue, 2 Jun 2026 22:55:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780440925; cv=none; b=pft/FMacATAZToLOFEyRLN97xIJcfzmRQS8qfaVbogEwwoa3+j4/dOuegwSkenRPNbjdR0z0YtGt+WqYdhPQiHpIWXfcNIEeqnU/e4ZnnupDTMZnjHX3fZIaQHCHydlZGyOquhiKW9ATmgeNllXJ281qOMMErOUNqeEaBwY/SIA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780440925; c=relaxed/simple; bh=Ru4IidLwglPuNPr+zL+XSfk1VOshaLc68K+tJfKnWfI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gYXM3QFyeZzcyXijjNkRON14WA0heqFiQHpYk1obKaE/47AxuUNypVgUqOBf79oFaiPJoUnMzemfOvXZLwoLIX9l13D3dDhFFA+o53fXkEK83U/zHxJtxJUM2v/4b1zjrIMPIB42kg9cSb9EHeHdZEpVxbjRPYoYhLrrI7qcCt8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PpJAeHav; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PpJAeHav" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780440924; x=1811976924; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ru4IidLwglPuNPr+zL+XSfk1VOshaLc68K+tJfKnWfI=; b=PpJAeHav/bEuiB7QL+/xWl9lrkimiKhAbkuyY8HhczFFHBSt5dpXT2XT ApsxcmJc8FyylaTz49+39Z3P2zI9zALUVvw98KnZmz4apx5MK0kZ9y0Sd K+ssv3VQoQXZSJRilBQjp2ByLKgFQiwqUbhP7fKshyYRzZh4zeuES5m4W E9YKccYrof+epDLzlPe3ssLytyW62y5LtqELdJ1MFYtw2LgKp2z43OWe3 QoimHJfKuKo5U/QKuMGB22M1z0A0+I7nO32wJOnbk3g2deX7L5j59qsLR VYqo4thQ/+r6J5G8WR/0eygetr8Ui7au4bBbugAPyJYGzHu/oCymu4S+d g==; X-CSE-ConnectionGUID: 7MK85ZfZSxSYQMxIiZaLfQ== X-CSE-MsgGUID: v6EiISMjRKmmmtqjkx0teg== X-IronPort-AV: E=McAfee;i="6800,10657,11805"; a="81421407" X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="81421407" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 15:55:21 -0700 X-CSE-ConnectionGUID: hPnJ3kpQSwWfzbHuCuVKiQ== X-CSE-MsgGUID: GGv72299STSZFvIu0OTlNQ== X-ExtLoop1: 1 Received: from anguy11-upstream.jf.intel.com ([10.166.9.133]) by fmviesa003.fm.intel.com with ESMTP; 02 Jun 2026 15:55:20 -0700 From: Tony Nguyen To: davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com, edumazet@google.com, andrew+netdev@lunn.ch, netdev@vger.kernel.org Cc: Petr Oros , anthony.l.nguyen@intel.com, arkadiusz.kubalewski@intel.com, przemyslaw.kitszel@intel.com, horms@kernel.org, Aleksandr Loktionov , Paul Menzel , Rinitha S Subject: [PATCH net 2/3] ice: fix missing priority callbacks for U.FL DPLL pins Date: Tue, 2 Jun 2026 15:55:10 -0700 Message-ID: <20260602225513.393338-3-anthony.l.nguyen@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260602225513.393338-1-anthony.l.nguyen@intel.com> References: <20260602225513.393338-1-anthony.l.nguyen@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Petr Oros The U.FL2 input pin advertises DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE in its capability mask, but ice_dpll_pin_ufl_ops does not provide .prio_get and .prio_set callbacks. As a result the DPLL subsystem cannot report or accept priority for U.FL pins: pin-get omits the prio field on U.FL2 and pin-set with prio is rejected as invalid, even though the capability is present. This prevents user space from using priority to select or disable U.FL2 as a DPLL input source. Reproducer with iproute2 (dpll command): # dpll pin show board-label U.FL2 pin id 16: module-name ice board-label U.FL2 type ext capabilities priority-can-change|state-can-change parent-device: id 0 direction input state selectable phase-offset 0 /* note: no "prio" between "direction" and "state", even though priority-can-change is advertised */ # dpll pin set id 16 parent-device 0 prio 5 RTNETLINK answers: Operation not supported After the fix the prio field is reported by pin show and pin set with prio is accepted on U.FL2. Add the missing .prio_get and .prio_set callbacks to ice_dpll_pin_ufl_ops, reusing ice_dpll_sw_input_prio_{get,set}. The same ops struct is shared by U.FL1 and U.FL2: U.FL2 (input) delegates to the backing hardware input pin, while U.FL1 (output) does not advertise DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE so the dpll core capability gate never invokes prio_set for it, and prio_get reports the OUTPUT sentinel (ICE_DPLL_PIN_PRIO_OUTPUT) on the output side exactly like the SMA path does today. Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control") Reviewed-by: Aleksandr Loktionov Reviewed-by: Paul Menzel Signed-off-by: Petr Oros Tested-by: Rinitha S (A Contingent worker at Intel) Signed-off-by: Tony Nguyen --- drivers/net/ethernet/intel/ice/ice_dpll.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c index 892bc7c2e28b..0704e92ab043 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -2633,6 +2633,8 @@ static const struct dpll_pin_ops ice_dpll_pin_ufl_ops = { .state_on_dpll_set = ice_dpll_ufl_pin_state_set, .state_on_dpll_get = ice_dpll_sw_pin_state_get, .direction_get = ice_dpll_pin_sw_direction_get, + .prio_get = ice_dpll_sw_input_prio_get, + .prio_set = ice_dpll_sw_input_prio_set, .frequency_get = ice_dpll_sw_pin_frequency_get, .frequency_set = ice_dpll_sw_pin_frequency_set, .esync_set = ice_dpll_sw_esync_set, -- 2.47.1