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Thu, 04 Jun 2026 18:01:11 -0700 (PDT) From: Alex Elder To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, maxime.chevallier@bootlin.com, rmk+kernel@armlinux.org.uk, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linusw@kernel.org, brgl@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org Cc: Daniel Thompson , elder@riscstar.com, mohd.anwar@oss.qualcomm.com, a0987203069@gmail.com, alexandre.torgue@foss.st.com, ast@kernel.org, boon.khai.ng@altera.com, chenchuangyu@xiaomi.com, chenhuacai@kernel.org, daniel@iogearbox.net, hawk@kernel.org, hkallweit1@gmail.com, inochiama@gmail.com, john.fastabend@gmail.com, julianbraha@gmail.com, livelycarpet87@gmail.com, mcoquelin.stm32@gmail.com, me@ziyao.cc, prabhakar.mahadev-lad.rj@bp.renesas.com, richardcochran@gmail.com, rohan.g.thomas@altera.com, sdf@fomichev.me, siyanteng@cqsoftware.com.cn, weishangjuan@eswincomputing.com, wens@kernel.org, netdev@vger.kernel.org, bpf@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 14/14] arm64: dts: qcom: qcs6490-rb3gen2: enable TC9564 with a single QCA8081 phy Date: Thu, 4 Jun 2026 20:00:21 -0500 Message-ID: <20260605010022.968612-15-elder@riscstar.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260605010022.968612-1-elder@riscstar.com> References: <20260605010022.968612-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Daniel Thompson The QCS6490 RB3Gen2 includes a Toshiba TC9564 (a.k.a. Qualcomm QPS615). TC9564 is an twin Ethernet-AVB/TSN bridge with an integrated PCIe switch. Downstream PCIe switch port 3 has an embedded PCIe endpoint, which includes two functions. The GPIO controller embedded within the TC9564 is accessed via memory-mapped I/O through the first PCIe function's BAR4. Both embedded PCIe functions have an attached Synopsys XGMAC, but not all RB3gen2 builds include PHYs on both ports. All versions include a TC9564 combined with a single QCA8081 attached to eMAC1. Add properties to the existing PCI nodes to describe how the TC9564 and QCA8081 are connected to each other (and to the host SoC). Signed-off-by: Daniel Thompson Co-developed-by: Alex Elder Signed-off-by: Alex Elder --- Checkpatch notes: - pci1179 is not a recognized vendor ID - Some lines are longer than recommented arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 48 ++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index e393ccf1884af..1d83b07360a33 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -308,6 +308,15 @@ vdd_ntn_1p8: regulator-vdd-ntn-1p8 { regulator-enable-ramp-delay = <10000>; }; + qep_1p8: regulator-qep-1p8 { + compatible = "regulator-fixed"; + regulator-name = "qep_1p8"; + gpio = <&pm7325_gpios 8 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + }; + wcn6750-pmu { compatible = "qcom,wcn6750-pmu"; pinctrl-0 = <&bt_en>; @@ -938,19 +947,51 @@ pcie@3,0 { bus-range = <0x5 0xff>; pci@0,0 { + compatible = "pci1179,0220"; reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; ranges; + + tc9564_gpio0: gpio { + gpio-controller; + #gpio-cells = <2>; + }; }; pci@0,1 { + compatible = "pci1179,0220"; reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; ranges; + + ethernet { + phy-mode = "sgmii"; + phy-handle = <&tc9564_emac1_phy>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + tc9564_emac1_phy: ethernet-phy@1c { + compatible = "ethernet-phy-id004d.d101"; + reg = <0x1c>; + snps,reset = <&tc9564_gpio0 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + + vdd18-supply = <&qep_1p8>; + + pinctrl-names = "default"; + pinctrl-0 = <&qep_irq_pin>; + interrupts-extended = <&tlmm 101 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; }; }; }; @@ -1524,6 +1565,13 @@ usb_hub_reset_state: usb-hub-reset-state { drive-strength = <2>; bias-disable; }; + + qep_irq_pin: qep-irq-state { + pins = "gpio101"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; &lpass_audiocc { -- 2.51.0