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Fri, 5 Jun 2026 11:11:09 -0700 From: Mark Bloch To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Jonathan Corbet , Shuah Khan , Jiri Pirko , Simon Horman , Sunil Goutham , Linu Cherian , Geetha sowjanya , hariprasad , Subbaraya Sundeep , Bharat Bhushan , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Borislav Petkov (AMD)" , Andrew Morton , Randy Dunlap , Thomas Gleixner , Petr Mladek , "Peter Zijlstra (Intel)" , "Dave Hansen" , Vlastimil Babka , Christian Brauner , Tejun Heo , Feng Tang , Dapeng Mi , "Kees Cook" , Marco Elver , Eric Biggers , Li RongQing , "Paul E. McKenney" , Ethan Nelson-Moore , , , , , Shay Drori Subject: [PATCH net-next V3 4/7] net/mlx5: Register devlink after device init Date: Fri, 5 Jun 2026 21:10:27 +0300 Message-ID: <20260605181030.3486619-5-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260605181030.3486619-1-mbloch@nvidia.com> References: <20260605181030.3486619-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C381:EE_|CH1PR12MB9695:EE_ X-MS-Office365-Filtering-Correlation-Id: 6045a40d-02cb-49f2-a72b-08dec32de69a X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|7416014|376014|1800799024|6133799003|11063799006|56012099006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: o4fbhzA25QUgCEHwdSy00KASEx6Tc4eTN3NTy8oMo712HINxIxGu18s6Gor+2aljzj0cPl64tF8PAv42IlSH6ZzohaVtD+0UbAA2N+rgtYNfhxbx6BwpQ88C3ziuceQpeSj8IWKERiQlL53OxdQFiFDXw1oeYeSvnC9Rt7yr8BTW1D8+1USsEDR6udPkWFc9uZtACrdXbWCPvz6MrnG5WSEjGpnmq8xOwCTMfPDL+itAkE7tSauOsXGECBvTDx00synvBYbjacnCmAAg++ge1/aEDFTEbUHOv695SSZemV8Tt62tipkzDguDlRQYoLAKfhHY8PdQSVud+f31SNXdehUcPdup15Y7PjPyV/TLkUdIN9jGI/TpiNdJB4yJhma6peQU+pxNbS6xwjaCZdGGuz2oCAydnrrEQeZMvDzMXpW5KMpLfh+N2q1nEhHXrSEQY+5pQLh/0fNyy/cdzdj+qlkUitqHSaP4CA7UwofrtfMxqML41IG2I8k5t73RWB2j6sYzK+L6PaGdMZIf4Mnc/qNJK2VYMDukOo/EYwYfwwnk26Xh13ADRoPHizNR0xSjErcXkURcVRgtcw+OWU7wIN9baKWR3oSjBp/9aIiw3+EKL694BuxZwZ8ubyGaYv6q8RnE0dzlNRnZJfXW1mhiGWk9BEfbMIiAZRH+MLrRFQbGqlRmAU4+5gsx12OlCklDBy8Oc5EYVSVzKDyuBZPJh2rXcIsmubO7inpPpbMlNOY= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(7416014)(376014)(1800799024)(6133799003)(11063799006)(56012099006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KaNePOcfClsobsO9LEVq79Zh3g2EZDM6LDc0KaiqLeO0ikGn78jQYGRmcN/t415WULiELP4ox27O+ieCF7u9IUzkFtL/QD++fSwQjacjNoFCbkm2H3Nm36D1bkkwMfWsSant6hFXeQ0CGc1bV7ClOiJkFnYCTuEgEEO/UGajXf3EoH99LEwn1opt2kEURQWnffHM3UECP/e3gUcqicJagbfhwKwaWZLK4wIYNgWuHgTvZtyIiCflhBZgahJo0yH/kV/PPt7tjss67PmQ0xUnx11dbkkea2O/uMQqGbH2roMjgVrnYLfafhtdgPWeGpPrYskZmk/tON4QdzHrlQM80oJrZFFBKLvWafbsszWA7oGnWFRqnauh1rLcGJ0/rsyLPHh6EGxQ0qdHeNDP9t+svtjbOyBKTRMqEqKGYJOrzjxxTjaEQYbOypUzEFSs/tpK X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 18:11:44.1890 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6045a40d-02cb-49f2-a72b-08dec32de69a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C381.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9695 devl_register() makes the devlink instance visible to userspace. A later patch also makes registration the point where devlink core may call eswitch_mode_set() to apply a boot-time default eswitch mode. Move mlx5 devlink registration after mlx5 device initialization completes, including the lightweight init path, so registration-time devlink operations see initialized driver state. Move devl_unregister() before the matching teardown paths, so unregister notifications are emitted from devl_unregister() before mlx5 removes the devlink objects. Add a devl-locked uninit helper so failed nested devlink setup can unwind the initialized device before the instance is registered. Reviewed-by: Shay Drori Signed-off-by: Mark Bloch --- .../net/ethernet/mellanox/mlx5/core/main.c | 34 ++++++++++++++----- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index fd285aeb9630..4e3cb6ec8630 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -1454,31 +1454,40 @@ int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev) return err; } +static void mlx5_uninit_one_devl_locked(struct mlx5_core_dev *dev); + int mlx5_init_one(struct mlx5_core_dev *dev) { struct devlink *devlink = priv_to_devlink(dev); int err; devl_lock(devlink); + err = mlx5_init_one_devl_locked(dev); + if (err) + goto unlock; + if (dev->shd) { err = devl_nested_devlink_set(dev->shd, devlink); if (err) - goto unlock; + goto err_uninit; } + devl_register(devlink); - err = mlx5_init_one_devl_locked(dev); - if (err) - devl_unregister(devlink); + devl_unlock(devlink); + return 0; + +err_uninit: + mlx5_uninit_one_devl_locked(dev); unlock: devl_unlock(devlink); return err; } -void mlx5_uninit_one(struct mlx5_core_dev *dev) +static void mlx5_uninit_one_devl_locked(struct mlx5_core_dev *dev) { struct devlink *devlink = priv_to_devlink(dev); - devl_lock(devlink); + devl_assert_locked(devlink); mutex_lock(&dev->intf_state_mutex); mlx5_hwmon_dev_unregister(dev); @@ -1501,7 +1510,15 @@ void mlx5_uninit_one(struct mlx5_core_dev *dev) mlx5_function_teardown(dev, true); out: mutex_unlock(&dev->intf_state_mutex); +} + +void mlx5_uninit_one(struct mlx5_core_dev *dev) +{ + struct devlink *devlink = priv_to_devlink(dev); + + devl_lock(devlink); devl_unregister(devlink); + mlx5_uninit_one_devl_locked(dev); devl_unlock(devlink); } @@ -1636,7 +1653,6 @@ int mlx5_init_one_light(struct mlx5_core_dev *dev) int err; devl_lock(devlink); - devl_register(devlink); dev->state = MLX5_DEVICE_STATE_UP; err = mlx5_function_enable(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); if (err) { @@ -1656,6 +1672,7 @@ int mlx5_init_one_light(struct mlx5_core_dev *dev) goto query_hca_caps_err; } + devl_register(devlink); devl_unlock(devlink); return 0; @@ -1663,7 +1680,6 @@ int mlx5_init_one_light(struct mlx5_core_dev *dev) mlx5_function_disable(dev, true); out: dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; - devl_unregister(devlink); devl_unlock(devlink); return err; } @@ -1673,8 +1689,8 @@ void mlx5_uninit_one_light(struct mlx5_core_dev *dev) struct devlink *devlink = priv_to_devlink(dev); devl_lock(devlink); - mlx5_devlink_params_unregister(priv_to_devlink(dev)); devl_unregister(devlink); + mlx5_devlink_params_unregister(priv_to_devlink(dev)); devl_unlock(devlink); if (dev->state != MLX5_DEVICE_STATE_UP) return; -- 2.34.1