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Fri, 5 Jun 2026 11:11:18 -0700 From: Mark Bloch To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Jonathan Corbet , Shuah Khan , Jiri Pirko , Simon Horman , Sunil Goutham , Linu Cherian , Geetha sowjanya , hariprasad , Subbaraya Sundeep , Bharat Bhushan , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Borislav Petkov (AMD)" , Andrew Morton , Randy Dunlap , Thomas Gleixner , Petr Mladek , "Peter Zijlstra (Intel)" , "Dave Hansen" , Vlastimil Babka , Christian Brauner , Tejun Heo , Feng Tang , Dapeng Mi , "Kees Cook" , Marco Elver , Eric Biggers , Li RongQing , "Paul E. McKenney" , Ethan Nelson-Moore , , , , Subject: [PATCH net-next V3 5/7] octeontx2-af: Register devlink after SR-IOV init Date: Fri, 5 Jun 2026 21:10:28 +0300 Message-ID: <20260605181030.3486619-6-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260605181030.3486619-1-mbloch@nvidia.com> References: <20260605181030.3486619-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW1PEPF0001615C:EE_|LV8PR12MB9230:EE_ X-MS-Office365-Filtering-Correlation-Id: 991af997-5fbe-437e-652b-08dec32de9e1 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700016|22082099003|18002099003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: WOD9XKmi1mIAlyrt3OuZnW2VlCIwrv/zsxf907axEY0+yJOeCNRA+PeIXhfi7ECKgExMHmqfqtkK0NGqwAMqUElbhClxoo7OlvAIGtbcArjs0xc7Bqiw2BSXlf4wzNhR3hQow4q5eS2X+nJcyjN62yWQDo9cShuKq0NmxTq23ud1m6EhYXT5CnO8FbIrA0vFVmZ+HYlKL8J4bEWFGKUgptmxvGiXr8u2imq6E7FDLeDo9LCoToE9VsDkslLo7uqMXGnWhpuMIrxA6cN6UHdr94ofzGdu4lL5MNETKBUUPzxQ9L0NrjxIpn9ojnSzh/CQr+NiajRb2A47r/hSg/gi+gDnwmiQl0BrnMYpJMZF7jASx3Or4ZaL4cTuktR17DaUYDd63TNvZBXq7MxM5rkZs6TyRkwbRDutUCxL5T3AlfoI3NgwvDtC0dfJbqnCGk7CkjQAoGz+t6I4i2GanQAHOEFwafQuiCEXcSyE4HPzVkQoX90z+N4wgx872HlyL1L0sKAUWJRraQ+hrNK3gRrWzCaNIY+nyQG3s81qsKW+rO7VZU0MOFdiex3w8Eudv0MEKWBkKV4kzC6bN+D5R46nkxy2O9Sr/gutFz+pzxmtw1xuJzpFdSxNeHuHetwJPww+1LW5pSaw0zoe5q5WI3q41ysQf/BtwUJmK+2B2IcD9Ad/Jw+UREsVWvBFRb+P8NuNUTvkhUqXFNE5DeWAKKYZqjtVuNQ4Vcwf+T5/YstHPdU= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(36860700016)(22082099003)(18002099003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5xC8XNgVSNoZmHewh6fhVtU6C42NyHorVq/57G0dBJ1m42T43NmoEyLdjOTnh+Za6FabFe+qm/lLNWP3fa+o4qlFPZKovMGPd3443EJDL8w8Zv7xRhSPD3D3ybj5r6+ee2PZIzqJeSprVDmYQdSneLywSS+UNp8IV/sum5xukNEmh1hJqBa4RaaQrWP3Ri2Ry4/JyBMAK/RwyIDkzjFeQ43edErrkNTOsLDfXUOR636jXD3Bqdh9b1CJMQOsVyzvIz7j8Tp1hzdTrdID21LhG9dWm5vfaaAJuYKWs8ws+Ah9xUkiV5IO+cOalj/Z7oMyh7U6O2N8YxfiVOuF6dLKq+l4AVftwYqMfPyd/GTnVGaIclfn/RF2w2FfLLleu7rNV6EvjhRO6lO/z4Hx2/rY40TLg+35NsHGbikHTbT0h3HJRYJLY3vwbmGuQmFBX9oH X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 18:11:49.7348 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 991af997-5fbe-437e-652b-08dec32de9e1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MW1PEPF0001615C.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9230 A later patch makes devlink registration the point where devlink core may call eswitch_mode_set() to apply a boot-time default eswitch mode. Move octeontx2 AF devlink registration after SR-IOV is enabled and the representor switch lock is initialized, so the AF eswitch mode set path sees the state it depends on. If devlink registration fails after SR-IOV setup, unregister interrupts before disabling SR-IOV. This keeps the AF-VF mailbox IRQ handlers synchronized before the AF-VF mailbox workqueue is destroyed. Signed-off-by: Mark Bloch --- .../net/ethernet/marvell/octeontx2/af/rvu.c | 24 ++++++++++--------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c index 3cf131508ecf..c2b52eb4ffab 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c @@ -3545,6 +3545,7 @@ static void rvu_update_module_params(struct rvu *rvu) static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct device *dev = &pdev->dev; + bool sriov_done = false; struct rvu *rvu; int err; @@ -3634,26 +3635,27 @@ static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) goto err_flr; } - err = rvu_register_dl(rvu); - if (err) { - dev_err(dev, "%s: Failed to register devlink\n", __func__); - goto err_irq; - } - rvu_setup_rvum_blk_revid(rvu); /* Enable AF's VFs (if any) */ err = rvu_enable_sriov(rvu); if (err) { dev_err(dev, "%s: Failed to enable sriov\n", __func__); - goto err_dl; + goto err_irq; + } + sriov_done = true; + + mutex_init(&rvu->rswitch.switch_lock); + + err = rvu_register_dl(rvu); + if (err) { + dev_err(dev, "%s: Failed to register devlink\n", __func__); + goto err_irq; } /* Initialize debugfs */ rvu_dbg_init(rvu); - mutex_init(&rvu->rswitch.switch_lock); - if (rvu->fwdata) ptp_start(rvu, rvu->fwdata->sclk, rvu->fwdata->ptp_ext_clk_rate, rvu->fwdata->ptp_ext_tstamp); @@ -3662,10 +3664,10 @@ static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) rvu_alloc_cint_qint_mem(rvu, &rvu->pf[RVU_AFPF], BLKADDR_NIX0, (rvu->hw->block[BLKADDR_NIX0].lf.max)); return 0; -err_dl: - rvu_unregister_dl(rvu); err_irq: rvu_unregister_interrupts(rvu); + if (sriov_done) + rvu_disable_sriov(rvu); err_flr: rvu_flr_wq_destroy(rvu); err_mbox: -- 2.34.1