[PATCH net-next v1 02/10] cxgb4: Add T7 chip type identification and HW constants

[Potnuri Bharat Teja <bharat@chelsio.com>]

Introduce the core chip identification infrastructure, hardware limits,
and register layout definitions required to support Chelsio T7 adapters.

Add the CHELSIO_T7 version constant, T7_A0/T7_B0 silicon revision
codes, revision range sentinels, and the is_t7 inline validation helper
to t4_chip_type.h to establish the foundational detection logic.

Extend the hardware specifications within t4_hw.h for the T7 design.
This includes increasing the maximum microprocessor cores to 8, expanding
internal buffer queue allocations to 16, sizing SGE context tracking
structures to 28 bytes, and updating CIM logic analyzer constraints.
Replace legacy flat FLASH constants with a flexible enum t4_flash_loc
table mechanism to allow per-adapter dynamic flash maps, while keeping
existing firmware load path constants for backward compatibility.

Refactor value parameters and field mappings in t4_values.h and t4_tcb.h
to match the T7 architecture. This standardizes mailbox ownership suffix
conventions, implements the narrower 4-bit T7 PCIe memory offset shift,
and inserts explicit tuple boundary markers and width definitions for
expanded hardware filter configurations. Finally, integrate new TCP
Control Block field macros to support advanced T7 TOE states.

Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
 .../net/ethernet/chelsio/cxgb4/t4_chip_type.h |  10 ++
 drivers/net/ethernet/chelsio/cxgb4/t4_hw.h    | 136 ++++++++++++------
 drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h   |  16 +++
 .../net/ethernet/chelsio/cxgb4/t4_values.h    |  15 +-
 4 files changed, 129 insertions(+), 48 deletions(-)

diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_chip_type.h b/drivers/net/ethernet/chelsio/cxgb4/t4_chip_type.h
index 721c77577ec5..444675436b01 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_chip_type.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_chip_type.h
@@ -39,6 +39,7 @@
 #define CHELSIO_T4		0x4
 #define CHELSIO_T5		0x5
 #define CHELSIO_T6		0x6
+#define CHELSIO_T7		0x7
 
 /* We code the Chelsio T4 Family "Chip Code" as a tuple:
  *
@@ -67,6 +68,11 @@ enum chip_type {
 	T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
 	T6_FIRST_REV	= T6_A0,
 	T6_LAST_REV	= T6_A0,
+
+	T7_A0 = CHELSIO_CHIP_CODE(CHELSIO_T7, 0),
+	T7_B0 = CHELSIO_CHIP_CODE(CHELSIO_T7, 1),
+	T7_FIRST_REV    = T7_A0,
+	T7_LAST_REV     = T7_B0,
 };
 
 static inline int is_t4(enum chip_type chip)
@@ -84,4 +90,8 @@ static inline int is_t6(enum chip_type chip)
 	return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6);
 }
 
+static inline int is_t7(enum chip_type chip)
+{
+	return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T7);
+}
 #endif /* __T4_CHIP_TYPE_H__ */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
index 63bc956d2037..6c7761b88ca6 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
@@ -54,13 +54,18 @@ enum {
 	MBOX_LEN        = 64,   /* mailbox size in bytes */
 	TRACE_LEN       = 112,  /* length of trace data and mask */
 	FILTER_OPT_LEN  = 36,   /* filter tuple width for optional components */
+	T7_PM_RX_CACHE_NSTATS = 27, /* # of PM Rx Cache stats in T7 */
+	MAX_UP_CORES    = 8,    /* Max # of uP cores that can be enabled */
 };
 
 enum {
 	CIM_NUM_IBQ    = 6,     /* # of CIM IBQs */
+	CIM_NUM_IBQ_T7 = 16,    /* # of CIM IBQs for T7 */
 	CIM_NUM_OBQ    = 6,     /* # of CIM OBQs */
 	CIM_NUM_OBQ_T5 = 8,     /* # of CIM OBQs for T5 adapter */
-	CIMLA_SIZE     = 2048,  /* # of 32-bit words in CIM LA */
+	CIM_NUM_OBQ_T7 = 16,    /* # of CIM OBQs for T7 adapter */
+	CIMLA_SIZE     = (256 * 8),  /* 256 rows * ceil(235/32) 32-bit words */
+	CIMLA_SIZE_T6  = (256 * 10), /* 256 rows * ceil(311/32) 32-bit words */
 	CIM_PIFLA_SIZE = 64,    /* # of 192-bit words in CIM PIF LA */
 	CIM_MALA_SIZE  = 64,    /* # of 160-bit words in CIM MA LA */
 	CIM_IBQ_SIZE   = 128,   /* # of 128-bit words in a CIM IBQ */
@@ -89,6 +94,7 @@ enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV };    /* mailbox owners */
 enum {
 	SGE_MAX_WR_LEN = 512,     /* max WR size in bytes */
 	SGE_CTXT_SIZE = 24,       /* size of SGE context */
+	SGE_CTXT_SIZE_T7 = 28,    /* size of SGE context for T7 */
 	SGE_NTIMERS = 6,          /* # of interrupt holdoff timer values */
 	SGE_NCOUNTERS = 4,        /* # of interrupt packet counter values */
 	SGE_NDBQTIMERS = 8,       /* # of Doorbell Queue Timer values */
@@ -199,89 +205,127 @@ struct rsp_ctrl {
 #define FLASH_MAX_SIZE(nsecs)	((nsecs) * SF_SEC_SIZE)
 
 enum {
+	FLASH_FW_START_SEC = 8,
+	FLASH_FW_NSECS = 16,
+	FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
+	FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
+
+	FLASH_CFG_START_SEC = 31,
+	FLASH_CFG_NSECS = 1,
+	FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
+	FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
+
+	FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
+};
+
+enum t4_flash_loc {
 	/*
 	 * Various Expansion-ROM boot images, etc.
 	 */
-	FLASH_EXP_ROM_START_SEC = 0,
-	FLASH_EXP_ROM_NSECS = 6,
-	FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
-	FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
+	FLASH_LOC_EXP_ROM = 0,
 
 	/*
 	 * iSCSI Boot Firmware Table (iBFT) and other driver-related
 	 * parameters ...
 	 */
-	FLASH_IBFT_START_SEC = 6,
-	FLASH_IBFT_NSECS = 1,
-	FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
-	FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
+	FLASH_LOC_IBFT,
 
 	/*
 	 * Boot configuration data.
 	 */
-	FLASH_BOOTCFG_START_SEC = 7,
-	FLASH_BOOTCFG_NSECS = 1,
-	FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
-	FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
+	FLASH_LOC_BOOTCFG,
 
 	/*
 	 * Location of firmware image in FLASH.
 	 */
-	FLASH_FW_START_SEC = 8,
-	FLASH_FW_NSECS = 16,
-	FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
-	FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
+	FLASH_LOC_FW,
 
 	/* Location of bootstrap firmware image in FLASH.
 	 */
-	FLASH_FWBOOTSTRAP_START_SEC = 27,
-	FLASH_FWBOOTSTRAP_NSECS = 1,
-	FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC),
-	FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS),
+	FLASH_LOC_FWBOOTSTRAP,
 
 	/*
 	 * iSCSI persistent/crash information.
 	 */
-	FLASH_ISCSI_CRASH_START_SEC = 29,
-	FLASH_ISCSI_CRASH_NSECS = 1,
-	FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
-	FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
+	FLASH_LOC_ISCSI_CRASH,
 
 	/*
 	 * FCoE persistent/crash information.
 	 */
-	FLASH_FCOE_CRASH_START_SEC = 30,
-	FLASH_FCOE_CRASH_NSECS = 1,
-	FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
-	FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
+	FLASH_LOC_FCOE_CRASH,
 
 	/*
-	 * Location of Firmware Configuration File in FLASH.  Since the FPGA
-	 * "FLASH" is smaller we need to store the Configuration File in a
-	 * different location -- which will overlap the end of the firmware
-	 * image if firmware ever gets that large ...
+	 * Location of Firmware Configuration File in FLASH.
 	 */
-	FLASH_CFG_START_SEC = 31,
-	FLASH_CFG_NSECS = 1,
-	FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
-	FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
+	FLASH_LOC_CFG,
 
-	/* We don't support FLASH devices which can't support the full
-	 * standard set of sections which we need for normal
-	 * operations.
+	/*
+	 * CUDBG chip dump.
 	 */
-	FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
+	FLASH_LOC_CUDBG,
 
-	FLASH_FPGA_CFG_START_SEC = 15,
-	FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
+	/*
+	 * FW chip dump.
+	 */
+	FLASH_LOC_CHIP_DUMP,
 
 	/*
-	 * Sectors 32-63 are reserved for FLASH failover.
+	 * DPU boot information store.
 	 */
+	FLASH_LOC_DPU_BOOT,
+
+	/*
+	 * DPU peristent information store.
+	 */
+	FLASH_LOC_DPU_AREA,
+
+	/*
+	 * VPD location.
+	 */
+	FLASH_LOC_VPD,
+
+	/*
+	 * Backup init/vpd.
+	 */
+	FLASH_LOC_VPD_BACKUP,
+
+	/*
+	 * Sectors 32-63 for CUDBG.
+	 * Backup firmware image.
+	 */
+	FLASH_LOC_FW_BACKUP,
+
+	/*
+	 * Backup bootstrap firmware image.
+	 */
+	FLASH_LOC_FWBOOTSTRAP_BACKUP,
+
+	/*
+	 * Backup Location of Firmware Configuration File in FLASH.
+	 */
+	FLASH_LOC_CFG_BACK,
+
+	/*
+	 * Helper to retrieve info that spans the entire Boot related area.
+	 */
+	FLASH_LOC_BOOT_AREA,
+
+	/*
+	 * Helper to determine minimum standard set of sections needed for
+	 * normal operations.
+	 */
+	FLASH_LOC_MIN_SIZE,
+
+	/*
+	 * End of FLASH regions.
+	 */
+	FLASH_LOC_END
 };
 
-#undef FLASH_START
-#undef FLASH_MAX_SIZE
+struct t4_flash_loc_entry {
+	u16 start_sec;
+	u16 nsecs;
+};
 
 #define SGE_TIMESTAMP_S 0
 #define SGE_TIMESTAMP_M 0xfffffffffffffffULL
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h b/drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h
index 22a0220123ad..1b7fc71dd835 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h
@@ -141,4 +141,20 @@
 #define TF_NON_OFFLOAD_V(x)	((x) << TF_NON_OFFLOAD_S)
 #define TF_NON_OFFLOAD_F	TF_NON_OFFLOAD_V(1)
 
+#define TCB_T_RTT_TS_RECENT_AGE_W    6
+#define TCB_T_RTT_TS_RECENT_AGE_S    0
+#define TCB_T_RTT_TS_RECENT_AGE_M    0xffffffffULL
+#define TCB_T_RTT_TS_RECENT_AGE_V(x) ((x) << TCB_T_RTT_TS_RECENT_AGE_S)
+
+#define TF_MIGRATING_S    0
+#define TF_MIGRATING_V(x) ((x) << TF_MIGRATING_S)
+
+#define TF_RECV_TSTMP_S    53
+#define TF_RECV_TSTMP_V(x) ((__u64)(x) << TF_RECV_TSTMP_S)
+
+#define TF_PEND_CTL1_S    56
+#define TF_PEND_CTL1_V(x) ((__u64)(x) << TF_PEND_CTL1_S)
+
+#define TF_PEND_CTL2_S    57
+#define TF_PEND_CTL2_V(x) ((__u64)(x) << TF_PEND_CTL2_S)
 #endif /* __T4_TCB_H */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
index eb1aa82149db..a23527db6c20 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
@@ -119,18 +119,26 @@
 
 /* CIM register field values.
  */
-#define X_MBOWNER_FW			1
-#define X_MBOWNER_PL			2
+#define MBOWNER_FW_X			1
+#define MBOWNER_PL_X			2
 
 /* PCI-E definitions */
 #define WINDOW_SHIFT_X		10
 #define PCIEOFST_SHIFT_X	10
+#define T7_MEMOFST_SHIFT_X	4
 
 /* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
  * Compressed Filter Tuple for LE filters.  Each bit set in TP_VLAN_PRI_MAP
  * selects for a particular field being present.  These fields, when present
  * in the Compressed Filter Tuple, have the following widths in bits.
  */
+#define FT_FIRST_S                      FCOE_S
+#define FT_LAST_S                       FRAGMENTATION_S
+
+#define T7_FT_FIRST_S                   IPSECIDX_S
+#define T7_FT_LAST_S                    TCPFLAGS_S
+
+#define FT_IPSECIDX_W                   12
 #define FT_FCOE_W                       1
 #define FT_PORT_W                       3
 #define FT_VNIC_ID_W                    17
@@ -141,6 +149,9 @@
 #define FT_MACMATCH_W                   9
 #define FT_MPSHITTYPE_W                 3
 #define FT_FRAGMENTATION_W              1
+#define FT_ROCE_W			1
+#define FT_SYNONLY_W			1
+#define FT_TCPFLAGS_W			12
 
 /* Some of the Compressed Filter Tuple fields have internal structure.  These
  * bit shifts/masks describe those structures.  All shifts are relative to the
-- 
2.39.1