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Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni , Subject: [PATCH net-next v3 2/2] net: lan743x: add support for RMII interface Date: Mon, 8 Jun 2026 15:34:35 +0530 Message-ID: <20260608100435.11214-3-thangaraj.s@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260608100435.11214-1-thangaraj.s@microchip.com> References: <20260608100435.11214-1-thangaraj.s@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Enable RMII interface in the lan743x driver for PHY and MAC configuration. - Select RMII interface in lan743x_phy_interface_select(). - Update phylink supported_interfaces and MAC capabilities. - Enable RMII via RMII_CTL in lan743x_hardware_init(). - Define RMII_CTL register and enable bit in lan743x_main.h. EEE is not supported with RMII on PCI11x1x: the hardware does not implement LPI signaling over RMII. Clear RMII from lpi_interfaces to prevent phylink from enabling EEE on this interface. Signed-off-by: Thangaraj Samynathan --- Changes in v3: - Update commit message to document that EEE is disabled by setting lpi_capabilities = 0 Changes in v2: - Remove redundant mac_capabilities &= ~MAC_1000FD; phylink already handles capability reduction for RMII via phy_caps_from_interface() drivers/net/ethernet/microchip/lan743x_main.c | 17 +++++++++++++++++ drivers/net/ethernet/microchip/lan743x_main.h | 3 +++ 2 files changed, 20 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan743x_main.c b/drivers/net/ethernet/microchip/lan743x_main.c index 0798f3f1f435..ad3f833c8d86 100644 --- a/drivers/net/ethernet/microchip/lan743x_main.c +++ b/drivers/net/ethernet/microchip/lan743x_main.c @@ -1402,6 +1402,8 @@ static void lan743x_phy_interface_select(struct lan743x_adapter *adapter) if (adapter->is_pci11x1x && adapter->is_sgmii_en) adapter->phy_interface = PHY_INTERFACE_MODE_SGMII; + else if (adapter->is_pci11x1x && adapter->is_rmii_en) + adapter->phy_interface = PHY_INTERFACE_MODE_RMII; else if (id_rev == ID_REV_ID_LAN7430_) adapter->phy_interface = PHY_INTERFACE_MODE_GMII; else if ((id_rev == ID_REV_ID_LAN7431_) && (data & MAC_CR_MII_EN_)) @@ -3190,6 +3192,12 @@ static int lan743x_phylink_create(struct lan743x_adapter *adapter) __set_bit(PHY_INTERFACE_MODE_MII, adapter->phylink_config.supported_interfaces); break; + case PHY_INTERFACE_MODE_RMII: + __set_bit(PHY_INTERFACE_MODE_RMII, + adapter->phylink_config.supported_interfaces); + adapter->phylink_config.lpi_capabilities = 0; + break; + default: phy_interface_set_rgmii(adapter->phylink_config.supported_interfaces); } @@ -3197,6 +3205,9 @@ static int lan743x_phylink_create(struct lan743x_adapter *adapter) memcpy(adapter->phylink_config.lpi_interfaces, adapter->phylink_config.supported_interfaces, sizeof(adapter->phylink_config.lpi_interfaces)); + if (adapter->phy_interface == PHY_INTERFACE_MODE_RMII) + __clear_bit(PHY_INTERFACE_MODE_RMII, + adapter->phylink_config.lpi_interfaces); pl = phylink_create(&adapter->phylink_config, NULL, adapter->phy_interface, &lan743x_phylink_mac_ops); @@ -3541,6 +3552,7 @@ static int lan743x_hardware_init(struct lan743x_adapter *adapter, { struct lan743x_tx *tx; u32 sgmii_ctl; + u32 rmii_ctl; int index; int ret; @@ -3562,6 +3574,11 @@ static int lan743x_hardware_init(struct lan743x_adapter *adapter, sgmii_ctl |= SGMII_CTL_SGMII_POWER_DN_; } lan743x_csr_write(adapter, SGMII_CTL, sgmii_ctl); + if (adapter->is_rmii_en) { + rmii_ctl = lan743x_csr_read(adapter, RMII_CTL); + rmii_ctl |= RMII_CTL_RMII_ENABLE_; + lan743x_csr_write(adapter, RMII_CTL, rmii_ctl); + } } else { adapter->max_tx_channels = LAN743X_MAX_TX_CHANNELS; adapter->used_tx_channels = LAN743X_USED_TX_CHANNELS; diff --git a/drivers/net/ethernet/microchip/lan743x_main.h b/drivers/net/ethernet/microchip/lan743x_main.h index 1f8d9294a6ef..d9495cf96b41 100644 --- a/drivers/net/ethernet/microchip/lan743x_main.h +++ b/drivers/net/ethernet/microchip/lan743x_main.h @@ -325,6 +325,9 @@ #define MAC_WUCSR2_IPV6_TCPSYN_RCD_ BIT(5) #define MAC_WUCSR2_IPV4_TCPSYN_RCD_ BIT(4) +#define RMII_CTL (0x710) +#define RMII_CTL_RMII_ENABLE_ BIT(0) + #define SGMII_ACC (0x720) #define SGMII_ACC_SGMII_BZY_ BIT(31) #define SGMII_ACC_SGMII_WR_ BIT(30) -- 2.34.1