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Wed, 10 Jun 2026 04:55:32 -0700 (PDT) From: To: CC: , , , , , , , , Sukhdeep Singh Subject: [PATCH net-next v5 8/12] net: atlantic: add AQC113 PTP traffic class and TX path setup Date: Wed, 10 Jun 2026 17:24:44 +0530 Message-ID: <20260610115448.272-9-sukhdeeps@marvell.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260610115448.272-1-sukhdeeps@marvell.com> References: <20260610115448.272-1-sukhdeeps@marvell.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEwMDExMiBTYWx0ZWRfXxwlKbksk6wXd 0RSvSVBmoBPqgLrG+X67YjxF/MBzUzMM0Bzh2JA0UxEVLrsF1W/wzbeK6Z1EFBVWauQQxziMj/S s8Lql+r7Hs66qoTcwwAiOBvZKZAOimLKaHdFad/IJjfkcToR5FSr+182bqCRAgZhWD667sNDAse Jrgn+96NKTsQg2fPio3hwYzEF/i3zaCi0mYyNaqrEcB7YiY7steJOIdbD3qZIrfxntyY6KAWmYz fcP+1o/3FgtS9ZsqAU4xFHVtqYYIQNisalXA5zOA2YdGIPYxftsrIB5aZMLUCYv2KA0ApQTy53j rgtrrFJ/xqFUj688iLGm5ZgW4QfRWp9wyBxNkszM5XmbkC8QAG9K8S9vb3Fb23yGLFu36pvQaYI VAgLFqug/mfhBTHx9zjINNnqUA4OBBFTYZuDICEcsbR/NhC5BQ7Ql3eQqFv3oUjDGQcWxv5orhZ 8p+ki4DhaQx+8tSFpmg== X-Authority-Analysis: v=2.4 cv=Y6zIdBeN c=1 sm=1 tr=0 ts=6a2950ba cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=EAYMVhzMl8SCOHhVQcBL:22 a=M5GUcnROAAAA:8 a=Dpi8SI6RF_br7PiJ-gsA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: bw8U1Nyqqi76s4Wiq77BdrQerDeQFfAX X-Proofpoint-ORIG-GUID: bw8U1Nyqqi76s4Wiq77BdrQerDeQFfAX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-10_02,2026-06-09_02,2025-10-01_01 From: Sukhdeep Singh Add PTP traffic class (TC) buffer reservation and TX path improvements for AQC113: - Reserve dedicated TX and RX buffer space for PTP TC when PTP is enabled, reducing user TC buffers accordingly (TX: 8KB, RX: 16KB). - Configure PTP TC with no flow control and highest priority scheduling to ensure timely PTP packet transmission. TX path improvements: - Increase TX data and descriptor read-request limits when firmware has already enabled extended PCIe tag mode. Also simplify RSS queue calculation in hw_atl2_hw_rss_set() by extracting to a local variable and use unsigned types for loop variables to match their usage. Signed-off-by: Sukhdeep Singh --- .../aquantia/atlantic/hw_atl2/hw_atl2.c | 49 ++++++++++++++++--- .../atlantic/hw_atl2/hw_atl2_internal.h | 4 +- 2 files changed, 46 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c index a8ab27367dc1..39d84576ca51 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c @@ -151,6 +151,24 @@ static int hw_atl2_hw_reset(struct aq_hw_s *self) return err; } +static int hw_atl2_tc_ptp_set(struct aq_hw_s *self) +{ + /* Init TC2 for PTP_TX */ + hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, HW_ATL2_PTP_TXBUF_SIZE, + AQ_HW_PTP_TC); + + /* Init TC2 for PTP_RX */ + hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, HW_ATL2_PTP_RXBUF_SIZE, + AQ_HW_PTP_TC); + + /* No flow control for PTP */ + hw_atl_rpb_rx_xoff_en_per_tc_set(self, 0U, AQ_HW_PTP_TC); + + hw_atl2_tpb_tps_highest_priority_tc_set(self, AQ_HW_PTP_TC); + + return aq_hw_err_from_flags(self); +} + static int hw_atl2_hw_queue_to_tc_map_set(struct aq_hw_s *self) { struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; @@ -209,6 +227,11 @@ static int hw_atl2_hw_qos_set(struct aq_hw_s *self) unsigned int prio = 0U; u32 tc = 0U; + if (cfg->is_ptp) { + tx_buff_size -= HW_ATL2_PTP_TXBUF_SIZE; + rx_buff_size -= HW_ATL2_PTP_RXBUF_SIZE; + } + /* TPS Descriptor rate init */ hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U); hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA); @@ -242,6 +265,9 @@ static int hw_atl2_hw_qos_set(struct aq_hw_s *self) hw_atl_b0_set_fc(self, self->aq_nic_cfg->fc.req, tc); } + if (cfg->is_ptp) + hw_atl2_tc_ptp_set(self); + /* QoS 802.1p priority -> TC mapping */ for (prio = 0; prio < 8; ++prio) hw_atl_rpf_rpb_user_priority_tc_map_set(self, prio, @@ -259,8 +285,9 @@ static int hw_atl2_hw_rss_set(struct aq_hw_s *self, u8 *indirection_table = rss_params->indirection_table; const u32 num_tcs = aq_hw_num_tcs(self); u32 rpf_redir2_enable; - int tc; - int i; + u32 queue; + u32 tc; + u32 i; rpf_redir2_enable = num_tcs > 4 ? 1 : 0; @@ -268,10 +295,9 @@ static int hw_atl2_hw_rss_set(struct aq_hw_s *self, for (i = HW_ATL2_RSS_REDIRECTION_MAX; i--;) { for (tc = 0; tc != num_tcs; tc++) { - hw_atl2_new_rpf_rss_redir_set(self, tc, i, - tc * - aq_hw_q_per_tc(self) + - indirection_table[i]); + queue = tc * aq_hw_q_per_tc(self) + + indirection_table[i]; + hw_atl2_new_rpf_rss_redir_set(self, tc, i, queue); } } @@ -415,9 +441,20 @@ static int hw_atl2_hw_init_tx_path(struct aq_hw_s *self) hw_atl2_tpb_tx_buf_clk_gate_en_set(self, 0U); + if (hw_atl2_phi_ext_tag_get(self)) { + hw_atl2_tdm_tx_data_read_req_limit_set(self, 0x7F); + hw_atl2_tdm_tx_desc_read_req_limit_set(self, 0x0F); + } + return aq_hw_err_from_flags(self); } +/* Initialise new rx filters + * L2 promisc OFF + * VLAN promisc OFF + * + * User priority to TC + */ static void hw_atl2_hw_init_new_rx_filters(struct aq_hw_s *self) { u8 *prio_tc_map = self->aq_nic_cfg->prio_tc_map; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h index fc086d84fb91..31d7cae6641a 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h @@ -27,8 +27,10 @@ #define HW_ATL2_INT_MASK (0xFFFFFFFFU) #define HW_ATL2_TXBUF_MAX 128U -#define HW_ATL2_RXBUF_MAX 192U +#define HW_ATL2_PTP_TXBUF_SIZE 8U +#define HW_ATL2_RXBUF_MAX 192U +#define HW_ATL2_PTP_RXBUF_SIZE 16U #define HW_ATL2_RSS_REDIRECTION_MAX 64U #define HW_ATL2_TC_MAX 8U -- 2.43.0