From: Jakub Kicinski <kuba@kernel.org>
To: javen_xu@realsil.com.cn
Cc: Jakub Kicinski <kuba@kernel.org>,
hkallweit1@gmail.com, nic_swsd@realtek.com,
andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com,
pabeni@redhat.com, maxime.chevallier@bootlin.com,
horms@kernel.org, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH net-next v2 5/6] r8169: add ltr support for RTL8116af
Date: Sat, 13 Jun 2026 15:06:02 -0700 [thread overview]
Message-ID: <20260613220602.219782-1-kuba@kernel.org> (raw)
In-Reply-To: <20260611094345.880-6-javen_xu@realsil.com.cn>
This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.
---
r8169: add ltr support for RTL8116af
This patch adds ltr support for RTL8116af, enables RTL8116af enter l1.2
state. This makes sense for the system to enter c10 state.
> diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
> index a73c0215b2407..a49e7a8d8f4da 100644
> --- a/drivers/net/ethernet/realtek/r8169_main.c
> +++ b/drivers/net/ethernet/realtek/r8169_main.c
[ ... ]
> @@ -3153,8 +3155,22 @@ static void rtl_enable_ltr(struct rtl8169_private *tp)
> r8168_mac_ocp_write(tp, 0xcdf2, 0x9003);
> r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0000, LINK_SPEED_CHANGE_EN);
> break;
> - case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
> case RTL_GIGA_MAC_VER_52:
> + r8168_mac_ocp_write(tp, 0xcdd0, 0x9003);
> + r8168_mac_ocp_modify(tp, LTR_SNOOP, 0x0000, LTR_SNOOP_EN);
> + r8168_mac_ocp_write(tp, 0xe02c, 0x1880);
> + r8168_mac_ocp_write(tp, 0xe02e, 0x4880);
[Severity: High]
Does this completely redefine the LTR enable sequence for all devices using
RTL_GIGA_MAC_VER_52? Since older devices like RTL8117 also use this MAC
version, could this cause regressions for them by replacing the previous
fallthrough behavior? Should there be a check to ensure this only runs for
the newly added RTL8116af?
> + r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN);
> + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003);
> + r8168_mac_ocp_write(tp, 0xcdda, 0x9003);
> + r8168_mac_ocp_write(tp, 0xcddc, 0x9003);
> + r8168_mac_ocp_write(tp, 0xcdd2, 0x883c);
> + r8168_mac_ocp_write(tp, 0xcdd4, 0x8c12);
> + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003);
> + r8168_mac_ocp_write(tp, 0xe0a6, 0x9003);
> + r8168_mac_ocp_write(tp, 0xe0a8, 0x9003);
> + break;
> + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
> r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN);
> RTL_W8(tp, COMBO_LTR_EXTEND, RTL_R8(tp, COMBO_LTR_EXTEND) | COMBO_LTR_EXTEND_EN);
> fallthrough;
> @@ -3174,6 +3190,7 @@ static void rtl_enable_ltr(struct rtl8169_private *tp)
> }
> /* chip can trigger LTR */
> r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0003, LTR_OBFF_LOCK_EN);
> + r8168_mac_ocp_modify(tp, SEND_LTR_MSG, 0x0000, LTR_MSG_EN);
[Severity: High]
This unconditionally modifies SEND_LTR_MSG at the end of rtl_enable_ltr(),
which is called for multiple MAC versions. Was it intended to apply globally
to all chips, or should this change also be restricted to RTL8116af?
> }
>
> static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
[ ... ]
> @@ -3732,7 +3751,9 @@ static void rtl_hw_start_8117(struct rtl8169_private *tp)
>
> rtl_eri_set_bits(tp, 0xd4, 0x0010);
>
> - rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
> + rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4000);
> +
> + r8168_mac_ocp_write(tp, 0xe098, 0xc302);
[Severity: High]
Since older devices also use rtl_hw_start_8117(), will applying these register
changes unconditionally to all RTL_GIGA_MAC_VER_52 devices affect the hardware
initialization of existing devices? Could we add a check to restrict these
tweaks specifically to RTL8116af?
>
> rtl_disable_rxdvgate(tp);
>
> @@ -3759,9 +3780,9 @@ static void rtl_hw_start_8117(struct rtl8169_private *tp)
> }
>
> r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0000);
> - r8168_mac_ocp_write(tp, 0xea80, 0x0003);
> - r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
> - r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
> + r8168_mac_ocp_write(tp, 0xea80, 0x0000);
> + r8168_mac_ocp_modify(tp, 0xe052, 0x0009, 0x0000);
> + r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x045f);
[Severity: High]
Like the changes above in rtl_hw_start_8117(), these magic register updates
will be applied to RTL8117 as well. Can this break link stability or ASPM
for existing devices by replacing their expected register values?
>
> r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
> r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
next prev parent reply other threads:[~2026-06-13 22:06 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-11 9:43 [PATCH net-next v2 0/6] r8169: add support for phylink javen
2026-06-11 9:43 ` [PATCH net-next v2 1/6] r8169: add speed in private struct javen
2026-06-11 9:43 ` [PATCH net-next v2 2/6] r8169: create a virtual interrupt for linkchg javen
2026-06-13 22:05 ` Jakub Kicinski
2026-06-13 22:06 ` Jakub Kicinski
2026-06-11 9:43 ` [PATCH net-next v2 3/6] r8169: add support for phylink javen
2026-06-12 8:13 ` Maxime Chevallier
2026-06-13 22:05 ` Jakub Kicinski
2026-06-13 22:06 ` Jakub Kicinski
2026-06-11 9:43 ` [PATCH net-next v2 4/6] r8169: add support for RTL8116af javen
2026-06-13 22:06 ` Jakub Kicinski
2026-06-13 22:06 ` Jakub Kicinski
2026-06-11 9:43 ` [PATCH net-next v2 5/6] r8169: add ltr " javen
2026-06-13 22:06 ` Jakub Kicinski [this message]
2026-06-13 22:06 ` Jakub Kicinski
2026-06-11 9:43 ` [PATCH net-next v2 6/6] r8169: fix RTL8116af can not enter s0idle and c10 javen
2026-06-13 22:06 ` Jakub Kicinski
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