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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 55DCA3F7041; Mon, 29 Jun 2026 19:47:27 -0700 (PDT) From: Ratheesh Kannoth To: , CC: , , , , , , "Ratheesh Kannoth" Subject: [PATCH net-next 1/9] octeontx2-af: switch: Add AF to switch mbox and skeleton files Date: Tue, 30 Jun 2026 08:17:07 +0530 Message-ID: <20260630024715.4124281-2-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260630024715.4124281-1-rkannoth@marvell.com> References: <20260630024715.4124281-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: rIg4qPFBHj6WO1uiM0_s8lh4_vk0N6Ub X-Proofpoint-Spam-Info: AW1haW4tMjYwNjMwMDAyNCBTYWx0ZWRfX/N7r8GoRn+Z5 HXLkseXxxghmnY76IPUH1zxujONVRrpsMXy4oN8dttBcQve3BOJkTzEHE+Bu8qxXmHIbMVT9FDh Vj8z1r9fSdA/zXosqORWvFCNsQuFY7s= X-Authority-Analysis: v=2.4 cv=e802j6p/ c=1 sm=1 tr=0 ts=6a432e42 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=QXcCYyLzdtTjyudCfB6f:22 a=M5GUcnROAAAA:8 a=Q9e_prp1UuIZLeogYfEA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: rIg4qPFBHj6WO1uiM0_s8lh4_vk0N6Ub X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjMwMDAyNCBTYWx0ZWRfX4Yf0w9nsijaW 4x9QeTG+tXPFAWv+pxUMMtrYiVyPdwWSQ9ALi3zn8qFPUx+mruT0InSDHi5v1t8QG/UEqAZSYT/ LnKXbgUXOSdyUiIQ6GONkhJk6XGV5C905jCK0bESVZf+zI3rrEKAtYIlXw7vbXIClotinrj1QCy iC6HTeiY1BOCWfYT7wyKTKRQWhd7Q4Z9DActZ5UjA00vbulZjBD11ORploptBXdbYkAUEokHtaj JDFHEUwK//ooFhp1wMzxTzlpEcuMsD4nUSiwY5/WMD4jXfFOoahG0GII/QuVOXrjpSfxbhWviyx 1lT4AZYahsGguhjPZxMV9qRFfXQuDmVSa3w3tTxGckgjzPxThg0l/HncSCKWeqTMf6g8ofEuYN1 JxLNiJ/fRBX5t5KgS8bzkaxf+hpbZQ8bqYWvsbuupNpsagDZdxTelOJUfKAJxBsuAPag9n/VsHH cKftgX0U1LXhKG2Qb9g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-30_01,2026-06-26_01,2025-10-01_01 The Marvell switch hardware runs on a Linux OS. This OS receives various messages, which are parsed to create flow rules that can be installed on HW. The switch is capable of accelerating both L2 and L3 flows. This commit adds various mailbox messages used by the Linux OS (on arm64) to send events to the switch hardware. fdb messages: Linux bridge FDB messages fib messages: Linux routing table messages status messages: Packet status updates sent to Host Linux to keep flows active for connection-tracked flows. Signed-off-by: Ratheesh Kannoth --- .../ethernet/marvell/octeontx2/af/Makefile | 3 +- .../net/ethernet/marvell/octeontx2/af/mbox.h | 104 ++++++++++++++++++ .../marvell/octeontx2/af/switch/rvu_sw_fl.c | 21 ++++ .../marvell/octeontx2/af/switch/rvu_sw_fl.h | 11 ++ .../marvell/octeontx2/af/switch/rvu_sw_l2.c | 14 +++ .../marvell/octeontx2/af/switch/rvu_sw_l2.h | 11 ++ .../marvell/octeontx2/af/switch/rvu_sw_l3.c | 14 +++ .../marvell/octeontx2/af/switch/rvu_sw_l3.h | 11 ++ 8 files changed, 188 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.h diff --git a/drivers/net/ethernet/marvell/octeontx2/af/Makefile b/drivers/net/ethernet/marvell/octeontx2/af/Makefile index 91b7d6e96a61..82dd387308c9 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/Makefile +++ b/drivers/net/ethernet/marvell/octeontx2/af/Makefile @@ -3,7 +3,7 @@ # Makefile for Marvell's RVU Admin Function driver # -ccflags-y += -I$(src) +ccflags-y += -I$(src) -I$(src)/switch/ obj-$(CONFIG_OCTEONTX2_MBOX) += rvu_mbox.o obj-$(CONFIG_OCTEONTX2_AF) += rvu_af.o @@ -12,5 +12,6 @@ rvu_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \ rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \ rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \ rvu_sdp.o rvu_npc_hash.o mcs.o mcs_rvu_if.o mcs_cnf10kb.o \ + switch/rvu_sw_l2.o switch/rvu_sw_l3.o switch/rvu_sw_fl.o\ rvu_rep.o cn20k/mbox_init.o cn20k/nix.o cn20k/debugfs.o \ cn20k/npa.o cn20k/npc.o diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h index 714e47f68d93..821895a7014e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -164,6 +164,14 @@ M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \ M(GET_REP_CNT, 0x00d, get_rep_cnt, msg_req, get_rep_cnt_rsp) \ M(ESW_CFG, 0x00e, esw_cfg, esw_cfg_req, msg_rsp) \ M(REP_EVENT_NOTIFY, 0x00f, rep_event_notify, rep_event, msg_rsp) \ +M(FDB_NOTIFY, 0x010, fdb_notify, \ + fdb_notify_req, msg_rsp) \ +M(FIB_NOTIFY, 0x011, fib_notify, \ + fib_notify_req, msg_rsp) \ +M(FL_NOTIFY, 0x012, fl_notify, \ + fl_notify_req, msg_rsp) \ +M(FL_GET_STATS, 0x013, fl_get_stats, \ + fl_get_stats_req, fl_get_stats_rsp) \ /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ @@ -1805,6 +1813,102 @@ struct rep_event { struct rep_evt_data evt_data; }; +#define FDB_ADD BIT_ULL(0) +#define FDB_DEL BIT_ULL(1) +#define FIB_CMD BIT_ULL(2) +#define FL_ADD BIT_ULL(3) +#define FL_DEL BIT_ULL(4) +#define DP_ADD BIT_ULL(5) + +struct fdb_notify_req { + struct mbox_msghdr hdr; + u64 flags; + u8 mac[ETH_ALEN]; +}; + +struct fib_entry { + u64 cmd; + u64 gw_valid : 1; + u64 mac_valid : 1; + u64 vlan_valid: 1; + u64 host : 1; + u64 bridge : 1; + u64 ipv6 : 1; + u16 vlan_tag; + u32 dst_len; + u8 dst6_plen; + u8 gw6_plen; + union { + u32 dst; + u32 dst6[4]; + }; + union { + u32 gw; + u32 gw6[4]; + }; + u16 port_id; + u8 nud_state; + u8 mac[ETH_ALEN]; +}; + +struct fib_notify_req { + struct mbox_msghdr hdr; + u16 cnt; + struct fib_entry entry[16]; +}; + +struct fl_tuple { + __be32 ip4src; + __be32 m_ip4src; + __be32 ip4dst; + __be32 m_ip4dst; + __be16 sport; + __be16 m_sport; + __be16 dport; + __be16 m_dport; + __be16 eth_type; + __be16 m_eth_type; + u8 proto; + u8 smac[6]; + u8 m_smac[6]; + u8 dmac[6]; + u8 m_dmac[6]; + u64 is_xdev_br : 1; + u64 is_indev_br : 1; + u64 uni_di : 1; + u16 in_pf; + u16 xmit_pf; + u64 features; + struct { /* FLOW_ACTION_MANGLE */ + u8 offset; + u8 type; + u32 mask; + u32 val; +#define MANGLE_ARR_SZ 9 + } mangle[MANGLE_ARR_SZ]; /* 2 for ETH, 1 for VLAN, 4 for IPv6, 2 for L4. */ +#define MANGLE_LAYER_CNT 4 + u8 mangle_map[MANGLE_LAYER_CNT]; /* 1 for ETH, 1 for VLAN, 1 for L3, 1 for L4 */ + u8 mangle_cnt; +}; + +struct fl_notify_req { + struct mbox_msghdr hdr; + unsigned long cookie; + u64 flags; + u64 features; + struct fl_tuple tuple; +}; + +struct fl_get_stats_req { + struct mbox_msghdr hdr; + unsigned long cookie; +}; + +struct fl_get_stats_rsp { + struct mbox_msghdr hdr; + u64 pkts_diff; +}; + struct flow_msg { unsigned char dmac[6]; unsigned char smac[6]; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c new file mode 100644 index 000000000000..1f8b82a84a5d --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ +#include "rvu.h" + +int rvu_mbox_handler_fl_get_stats(struct rvu *rvu, + struct fl_get_stats_req *req, + struct fl_get_stats_rsp *rsp) +{ + return 0; +} + +int rvu_mbox_handler_fl_notify(struct rvu *rvu, + struct fl_notify_req *req, + struct msg_rsp *rsp) +{ + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h new file mode 100644 index 000000000000..cf3e5b884f77 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ + +#ifndef RVU_SW_FL_H +#define RVU_SW_FL_H + +#endif diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c new file mode 100644 index 000000000000..5f805bfa81ed --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ +#include "rvu.h" + +int rvu_mbox_handler_fdb_notify(struct rvu *rvu, + struct fdb_notify_req *req, + struct msg_rsp *rsp) +{ + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h new file mode 100644 index 000000000000..ff28612150c9 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ + +#ifndef RVU_SW_L2_H +#define RVU_SW_L2_H + +#endif diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c new file mode 100644 index 000000000000..2b798d5f0644 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ +#include "rvu.h" + +int rvu_mbox_handler_fib_notify(struct rvu *rvu, + struct fib_notify_req *req, + struct msg_rsp *rsp) +{ + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.h b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.h new file mode 100644 index 000000000000..ac8c4f9ba5ac --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ + +#ifndef RVU_SW_L3_H +#define RVU_SW_L3_H + +#endif -- 2.43.0