From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from zg8tmtyylji0my4xnjeumjiw.icoremail.net (zg8tmtyylji0my4xnjeumjiw.icoremail.net [162.243.161.220]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 085A02222D9; Tue, 30 Jun 2026 06:33:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.161.220 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782801199; cv=none; b=PdCOmhJXeFZhFplIBO63rFkCbkLy8+FYhxLwbyj9HR4tzDOmNHGRVjAHewQlK5zZ+4rV4q/t/3r7LCgjn4s6i21mKJP8W792ittSOg4U3WT6CSZggIilzT3nMeCkuBBUccYVh/ojjVKy9r7UmT1Xvto9vprejdzJj0LGBV3cCbY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782801199; c=relaxed/simple; bh=0cdOsRjjWkvnWG5ya1nBN615An1iMqVOo7w0MiaJISI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=a1LNeZmT/FDylGUlYLBkPKh51sdDiKNstY+y/FkJYmhXnJYlxJaZ/ph3HvBtcNU6bJnGJm8fOkxycRQMkRmpWnJY25NUax1ikfXEZcaHDA+P6kvXp0jL6J4RItEyuSqi9NCB1Uf1t4g6Mvq0j///AaLTol/DoGGi4v3zMHTShGM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=162.243.161.220 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0004057DT.eswin.cn (unknown [10.11.96.26]) by app2 (Coremail) with SMTP id TQJkCgBne54LY0NqWRwwAA--.52745S2; Tue, 30 Jun 2026 14:32:44 +0800 (CST) From: lizhi2@eswincomputing.com To: devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maxime.chevallier@bootlin.com Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com, horms@kernel.org, lee@kernel.org, wens@kernel.org, Zhi Li Subject: [PATCH net-next v9 2/6] dt-bindings: ethernet: eswin: add EIC7700 eth1 RX clock inversion variant Date: Tue, 30 Jun 2026 14:32:39 +0800 Message-ID: <20260630063239.1158-1-lizhi2@eswincomputing.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260630063123.1118-1-lizhi2@eswincomputing.com> References: <20260630063123.1118-1-lizhi2@eswincomputing.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:TQJkCgBne54LY0NqWRwwAA--.52745S2 X-Coremail-Antispam: 1UD129KBjvJXoWxuF43Ww1DuF4rJryxJF18Krg_yoWrXFW5pF WDury8Gr18Xr4xJw4xJF10k3W3t397ury3Kr4kAF17X3Z8t3Z8XrWI9a45Ga4xur4UZFy3 WayYqF1Fyayqy3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r4a6rW5MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1U MIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTRMrWrDUUUU X-CM-SenderInfo: xol2xx2s6h245lqf0zpsxwx03jof0z/ From: Zhi Li The EIC7700 SoC integrates two GMAC instances. The eth1 MAC exhibits different RX clock sampling characteristics due to silicon-inherent timing behavior. The eth1 MAC has a fixed, non-configurable RX clock-to-data skew at the MAC input in the order of 4-5 ns. This cannot be compensated solely by the standard MAC internal delay configuration and PHY delay, and RX clock inversion is required at 1000Mbps for correct sampling. The eth1 TX path also includes a fixed silicon-inherent delay of approximately 2 ns. This delay is always present and cannot be disabled. It is therefore part of the effective transmit timing observed on the wire. For the eth1 variant, the valid tx-internal-delay-ps values include this fixed delay component. Consequently, the effective range becomes 2000-4540 ps (approximately 2000 ps fixed delay plus 0-2540 ps programmable delay). Introduce a dedicated compatible string "eswin,eic7700-qos-eth-clk-inversion" to represent the eth1 variant, allowing the driver to apply RX clock inversion only when required by hardware variant selection. This keeps SoC-level differentiation without exposing silicon-fixed skew as configurable device tree parameters. To reflect this, model the TX internal delay as a base 0-4540 ps range, and constrain valid values per compatible using conditional schema rules. Update the binding schema as follows: - Define tx-internal-delay-ps as a base range: 0-4540 ps - Add compatible-specific constraints using if/then rules: * eswin,eic7700-qos-eth: max 2540 ps * eswin,eic7700-qos-eth-clk-inversion: minimum 2000 ps (effective range 2000-4540 ps) No functional change for existing "eswin,eic7700-qos-eth" users. Signed-off-by: Zhi Li --- .../bindings/net/eswin,eic7700-eth.yaml | 51 ++++++++++++++++++- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml index 4e02fedae5c6..ba49fd6a086c 100644 --- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml @@ -20,16 +20,37 @@ select: contains: enum: - eswin,eic7700-qos-eth + - eswin,eic7700-qos-eth-clk-inversion required: - compatible allOf: - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + const: eswin,eic7700-qos-eth + then: + properties: + tx-internal-delay-ps: + maximum: 2540 + - if: + properties: + compatible: + contains: + const: eswin,eic7700-qos-eth-clk-inversion + then: + properties: + tx-internal-delay-ps: + minimum: 2000 properties: compatible: items: - - const: eswin,eic7700-qos-eth + - enum: + - eswin,eic7700-qos-eth + - eswin,eic7700-qos-eth-clk-inversion - const: snps,dwmac-5.20 reg: @@ -69,7 +90,7 @@ properties: tx-internal-delay-ps: minimum: 0 - maximum: 2540 + maximum: 4540 multipleOf: 20 eswin,hsp-sp-csr: @@ -140,3 +161,29 @@ examples: snps,wr_osr_lmt = <2>; }; }; + + ethernet@50410000 { + compatible = "eswin,eic7700-qos-eth-clk-inversion", "snps,dwmac-5.20"; + reg = <0x50410000 0x10000>; + interrupt-parent = <&plic>; + interrupts = <70>; + interrupt-names = "macirq"; + clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>, + <&d0_clock 194>; + clock-names = "axi", "cfg", "stmmaceth", "tx"; + resets = <&reset 94>; + reset-names = "stmmaceth"; + eswin,hsp-sp-csr = <&hsp_sp_csr 0x200 0x208 0x218 0x214 0x21c>; + phy-handle = <&gmac1_phy0>; + phy-mode = "rgmii-id"; + snps,aal; + snps,fixed-burst; + snps,tso; + snps,axi-config = <&stmmac_axi_setup_gmac1>; + + stmmac_axi_setup_gmac1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <2>; + snps,wr_osr_lmt = <2>; + }; + }; -- 2.25.1