From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 719FE3EFFA1; Tue, 30 Jun 2026 09:25:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782811527; cv=none; b=PpFq12+wY/Zyt0k+tO51qv4PzYCREZpKQNeesYMileQhOJgtM+ziR6vu7WGa3JfI/kZBTXs2jLOT0uY/d1D4kmEQrTEwbJ/xrf849KIbNjYtLlbkZUNWFyWV9bxFsI8XtIdA3/SmNn5BNAoQK0q9Gw7dGNMyfb6UETEERZfpDjo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782811527; c=relaxed/simple; bh=CATfLh2qcwvtEt0xhGS/F+244C0U3vHC+rHChgYecfU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=c21yDfORwqze3n3KbbuQ40x9rGRPamlAsNkE1XN5YAypFuY/caNNX80FjDlsZbyxWJxwt3PDefi9fP9dDBQpvL6lapMrmmoNyMfbqATrGS7kqZ7bjXgjFUyeCkdBxdvkcFVVYBUjvrxSSAqKHtugb1xMxzLp0KaOteGL0fWAlsc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=dfHcViRH; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="dfHcViRH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1782811525; x=1814347525; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CATfLh2qcwvtEt0xhGS/F+244C0U3vHC+rHChgYecfU=; b=dfHcViRHxf/ixlyR7WTn7w8VX+fPYwcXoA6qqGXQMbQvHoaHkzJbteHa pVdHx/h3WI2S7kp1+nzooiF6BQL+xu6DDyBkqySuwI66GfpoxKVRLDXy0 lS+L7f96Fd3KqR3gyxFjDi3Jw9epolvqMuEV86ChIrXjOZGWfHsjgGwzg dv0aduO2Xd2KfskoXVhztdHWg1AUBVbUFUCqWuBbdneHL31H2+nxtkkY2 B1ylY5U6/yKxaCD+bIUYyx7Y0D3/R0jCJr414CFQRLRzDkZGkYZ68Lc8T PqUyHxsS8Tkrcj+kjWN7HhtaYN5jJJ5sEHYBh/WVe0RGCHd88dnuhZ9dT Q==; X-CSE-ConnectionGUID: fhnAmLc5T9+l/mBXxyHOag== X-CSE-MsgGUID: o1CCMN6FQwSFWfK3NS64nw== X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="69114548" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2026 02:25:24 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Tue, 30 Jun 2026 02:25:23 -0700 Received: from che-ll-i67131.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 30 Jun 2026 02:25:14 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , CC: Manikandan Muralidharan Subject: [PATCH v4 3/7] mtd: spi-nor: sfdp: expose the SFDP as a read-only NVMEM device Date: Tue, 30 Jun 2026 14:54:02 +0530 Message-ID: <20260630092406.150587-4-manikandan.m@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260630092406.150587-1-manikandan.m@microchip.com> References: <20260630092406.150587-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Register the cached SFDP as a read-only NVMEM device rooted at the flash's "sfdp" child node, exposing it in on-flash byte order. This lets NVMEM cells reference any SFDP data: a fixed-layout for parameters at a known offset, or an nvmem-layout parser for vendor data whose location must be discovered at runtime. The device is only registered when an "sfdp" node is present in the device tree. Signed-off-by: Manikandan Muralidharan --- drivers/mtd/spi-nor/core.c | 5 +++ drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/sfdp.c | 83 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 89 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index ccf4396cdcd0..e04ba3e3dee9 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3204,6 +3204,11 @@ static int spi_nor_init_params(struct spi_nor *nor) spi_nor_init_params_deprecated(nor); } + /* Expose the SFDP as an NVMEM device. */ + ret = spi_nor_register_sfdp_nvmem(nor); + if (ret) + return ret; + ret = spi_nor_late_init_params(nor); if (ret) return ret; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index ba2d1a862c9d..0a6484298c5c 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -698,6 +698,7 @@ int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode, int spi_nor_check_sfdp_signature(struct spi_nor *nor); int spi_nor_parse_sfdp(struct spi_nor *nor); +int spi_nor_register_sfdp_nvmem(struct spi_nor *nor); static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) { diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 4600983cb579..2df818bca6b5 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -6,6 +6,8 @@ #include #include +#include +#include #include #include @@ -1612,3 +1614,84 @@ int spi_nor_parse_sfdp(struct spi_nor *nor) kfree(param_headers); return err; } + +static int spi_nor_sfdp_nvmem_read(void *priv, unsigned int offset, + void *val, size_t bytes) +{ + struct spi_nor *nor = priv; + struct sfdp *sfdp = nor->sfdp; + size_t sfdp_size = sfdp->num_dwords * sizeof(*sfdp->dwords); + + if (offset >= sfdp_size || bytes > sfdp_size - offset) + return -EINVAL; + + /* The cached SFDP is kept in on-flash (little-endian) byte order. */ + memcpy(val, (u8 *)sfdp->dwords + offset, bytes); + + return 0; +} + +static void spi_nor_sfdp_nvmem_put_np(void *data) +{ + of_node_put(data); +} + +/** + * spi_nor_register_sfdp_nvmem() - expose the SFDP as a read-only NVMEM device + * @nor: pointer to a 'struct spi_nor' + * + * Expose the whole SFDP, in on-flash byte order, as a read-only NVMEM device + * rooted at the flash's "sfdp" child node. This lets generic (fixed-layout) or + * vendor (nvmem-layout) cells reference any SFDP data. The device is only + * registered when an "sfdp" node is described in the device tree. + * + * Return: 0 on success or if there is nothing to do, -errno otherwise. + */ +int spi_nor_register_sfdp_nvmem(struct spi_nor *nor) +{ + struct device *dev = nor->dev; + struct nvmem_config config = { }; + struct nvmem_device *nvmem; + struct device_node *np; + int ret; + + if (!nor->sfdp) + return 0; + + np = of_get_child_by_name(dev_of_node(dev), "sfdp"); + if (!np) + return 0; + + /* + * Register the put before devm_nvmem_register() so it runs last on + * detach, after the NVMEM device that uses the node is gone. + */ + ret = devm_add_action_or_reset(dev, spi_nor_sfdp_nvmem_put_np, np); + if (ret) + return ret; + + config.dev = dev; + config.of_node = np; + config.name = "sfdp"; + config.id = NVMEM_DEVID_AUTO; + config.owner = THIS_MODULE; + config.read_only = true; + config.word_size = 1; + config.stride = 1; + config.size = (int)(nor->sfdp->num_dwords * sizeof(*nor->sfdp->dwords)); + config.reg_read = spi_nor_sfdp_nvmem_read; + config.priv = nor; + + nvmem = devm_nvmem_register(dev, &config); + if (IS_ERR(nvmem)) { + /* NVMEM support is optional. */ + if (PTR_ERR(nvmem) == -EOPNOTSUPP) + return 0; + return dev_err_probe(dev, PTR_ERR(nvmem), + "failed to register SFDP NVMEM device\n"); + } + + dev_dbg(dev, "exposed %d-byte SFDP as an NVMEM device\n", config.size); + + return 0; +} -- 2.43.0