From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 774C14921B2 for ; Wed, 1 Jul 2026 15:56:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.41 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782921415; cv=none; b=Ost4c453TL1IO/5+Hf4Hsu7WG3PiAAvxuSmMNmO3DIfJ5t/T0CqKH27A54SBQoV0KtY/XcIP0ybu9XxQSfkwWw4MJ9xIXMQU3o0T7Lj+EKVAVHYFkYqHvO9KTTmosibbTikxX5EjkzU52KYZCQUyRBRp0QTu2ehKVJWezQPZTPo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782921415; c=relaxed/simple; bh=sCR7LCduQulp62y3Ouz854y7aYy0BrQ6pXog8+b4Jd8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C5JwajnMze5RXhrTgTN/s4zBN05G66yxbYhrM6y9FKNil7JQ/FbVo9stpSVJoCEEn5Zd5himJGSIOknm8EfGPH/4xLhIPvWe9uUN/fPaXM1r72t8lkfREb5esu3J4kpfO7Mh+HxrXSLCnSoo+JHbRFzDii6rrY7B+WTa4KMRW3c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=mLGxtHa0; arc=none smtp.client-ip=209.85.216.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mLGxtHa0" Received: by mail-pj1-f41.google.com with SMTP id 98e67ed59e1d1-37fa06b39b4so515634a91.2 for ; Wed, 01 Jul 2026 08:56:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1782921413; x=1783526213; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KHAz6u3wdG+hZ6Dsr9mcpDC869qiGMxaGeFpJqp6Z1Y=; b=mLGxtHa07lsdOhdt4fJfIH1+5th72V3we+H0nhTYZby2faKBliI8b1IMrx0kP3KdCY MYdKjcEtNAZGzyWe/2qjRebgiVlfnV+IWlscHp8ZxEkixIqyI9X6Y9kkizH2HBoBc6Jj Kq+tZfT2KxUgXzAOeFT1DfkOm3zn9dlmCWGnwuKTGt8QT/wVjEfdUAjMrFmPYysv1ila d5AWCxbQkOhEd/I28LlaqVwTYPjTqX4xNYdkwlbx3FmGJr8wu4pdWgaB1TUF0bRa5SBU 9Jl2NBTfnHjZ2QnbPUYu/zY7t9723h3dkX5rUu7wiimB5+UQFq8K9XgzJDkC1+jSPdIZ c87A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782921413; x=1783526213; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=KHAz6u3wdG+hZ6Dsr9mcpDC869qiGMxaGeFpJqp6Z1Y=; b=QUmHcqonehvMfCI8vBTm2X1IpeyvPcWBl1YEMcMocbl3d2gQaz8qx+3pHCIZdC7VQI e5Cqeo50KZtUmQaoraQhJnuFszLDiBx0bua2swwn1VxGpbl/IWLq0a8vDFIB92tou+8R xvDqIu6xNFsWjT+cTKmVpm1f9QXj6mYGZm7H6USn97HtgOIDu9ZA63+ExeSLKquKVkPi xoI1aXwzqIXdgwuagdKvk/YA23Q6DSvfnPFiQytHYTsuNM5+J5kD9g7eRm5t0RdOzdxw UWpHPfNH2VoAHJ0muB+szmkxWvDvp2mC+JgchxLuHQa7J8yKd/IJCg5mt7iDYEp6Cf2/ S4MA== X-Gm-Message-State: AOJu0Yza0JbNWiQ52oOGA+fXihlNICwKXKHA8axt3/5CXkE/USTtk6n/ at4UtaexO2KHsk4MflOx1Bh7WZmm/EoiIo1HrY2otxBIn6FvKjUuceyENUuzx/0l X-Gm-Gg: AfdE7clvVDcgSFj52DxtySF5v76BFdd+jWd294TjsiPXjUnIfwa+EjeaSJnmDjtz9vQ NWlvgC/PTYx5+G0/tPwSzmlV4usLdWDgoFttm+ENLOgDVWebuk7taCyuCna+fE3ZZPfsFZwaKhw 8WiNjuEfWe9/6L6YhCod0NblfUw/XLqNnNfbWYYytig67HwFCdHYjrXmqeHsm+LqPL+VChGu2Sc KWKP83FQHmggQ7u3RbnrVWgbFzaicdFupISfCiHaJGAFEPrYiNSF66fwlWfaomSWE5X/8JuXi2u b4rmWPbr0q6QsmoAggWL2aFUOTCrduUaET0tDh5zjz3/NnsMfwZ4cvGJ2XpdMZFDn1tuvmakfVC ORjDxtSO0l1/wAXwqpJ+PLmgQ7o5wwO+y3BKgFrqPqQm62ASJ7HyuhP5IivROEwCbWsoByFadUT jraWqJO9+8RDG+SKf/+1mhAU/hSB1p510+7gZ4wYsXujw0ce9Y X-Received: by 2002:a17:90b:570c:b0:37f:c683:e643 with SMTP id 98e67ed59e1d1-380aa1d4cbbmr1847529a91.24.1782921412550; Wed, 01 Jul 2026 08:56:52 -0700 (PDT) Received: from d.home.yangfl.dn42 ([2a09:bac1:76a0:d30::4cf:38]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-380ce0cb40dsm142785a91.13.2026.07.01.08.56.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jul 2026 08:56:52 -0700 (PDT) From: David Yang To: netdev@vger.kernel.org Cc: David Yang , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-kernel@vger.kernel.org Subject: [PATCH net-next v3 2/3] net: dsa: motorcomm: Split SMI module Date: Wed, 1 Jul 2026 23:54:05 +0800 Message-ID: <20260701155519.273212-3-mmyangfl@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260701155519.273212-1-mmyangfl@gmail.com> References: <20260701155519.273212-1-mmyangfl@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit SMI operations are going to be used across different modules. Signed-off-by: David Yang Reviewed-by: Andrew Lunn --- drivers/net/dsa/motorcomm/Makefile | 1 + drivers/net/dsa/motorcomm/chip.c | 207 +---------------------------- drivers/net/dsa/motorcomm/smi.c | 157 ++++++++++++++++++++++ drivers/net/dsa/motorcomm/smi.h | 88 ++++++++++++ 4 files changed, 247 insertions(+), 206 deletions(-) create mode 100644 drivers/net/dsa/motorcomm/smi.c create mode 100644 drivers/net/dsa/motorcomm/smi.h diff --git a/drivers/net/dsa/motorcomm/Makefile b/drivers/net/dsa/motorcomm/Makefile index afd03be9fa35..6cea5313a444 100644 --- a/drivers/net/dsa/motorcomm/Makefile +++ b/drivers/net/dsa/motorcomm/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: ISC obj-$(CONFIG_NET_DSA_YT921X) += yt921x.o yt921x-objs := chip.o +yt921x-objs += smi.o diff --git a/drivers/net/dsa/motorcomm/chip.c b/drivers/net/dsa/motorcomm/chip.c index f070732845eb..6dee25b6754a 100644 --- a/drivers/net/dsa/motorcomm/chip.c +++ b/drivers/net/dsa/motorcomm/chip.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -27,6 +26,7 @@ #include #include "chip.h" +#include "smi.h" struct yt921x_mib_desc { unsigned int size; @@ -155,9 +155,6 @@ static const struct yt921x_info yt921x_infos[] = { #define YT921X_VID_UNWARE 4095 -#define YT921X_POLL_SLEEP_US 10000 -#define YT921X_POLL_TIMEOUT_US 100000 - /* The interval should be small enough to avoid overflow of 32bit MIBs. * * Until we can read MIBs from stats64 call directly (i.e. sleep @@ -196,208 +193,6 @@ static u32 ethaddr_lo2_to_u32(const unsigned char *addr) return (addr[4] << 8) | addr[5]; } -static int yt921x_reg_read(struct yt921x_priv *priv, u32 reg, u32 *valp) -{ - WARN_ON(!mutex_is_locked(&priv->reg_lock)); - - return priv->reg_ops->read(priv->reg_ctx, reg, valp); -} - -static int yt921x_reg_write(struct yt921x_priv *priv, u32 reg, u32 val) -{ - WARN_ON(!mutex_is_locked(&priv->reg_lock)); - - return priv->reg_ops->write(priv->reg_ctx, reg, val); -} - -static int -yt921x_reg_wait(struct yt921x_priv *priv, u32 reg, u32 mask, u32 *valp) -{ - u32 val; - int res; - int ret; - - ret = read_poll_timeout(yt921x_reg_read, res, - res || (val & mask) == *valp, - YT921X_POLL_SLEEP_US, YT921X_POLL_TIMEOUT_US, - false, priv, reg, &val); - if (ret) - return ret; - if (res) - return res; - - *valp = val; - return 0; -} - -static int -yt921x_reg_update_bits(struct yt921x_priv *priv, u32 reg, u32 mask, u32 val) -{ - int res; - u32 v; - u32 u; - - res = yt921x_reg_read(priv, reg, &v); - if (res) - return res; - - u = v; - u &= ~mask; - u |= val; - if (u == v) - return 0; - - return yt921x_reg_write(priv, reg, u); -} - -static int yt921x_reg_set_bits(struct yt921x_priv *priv, u32 reg, u32 mask) -{ - return yt921x_reg_update_bits(priv, reg, 0, mask); -} - -static int yt921x_reg_clear_bits(struct yt921x_priv *priv, u32 reg, u32 mask) -{ - return yt921x_reg_update_bits(priv, reg, mask, 0); -} - -static int -yt921x_reg_toggle_bits(struct yt921x_priv *priv, u32 reg, u32 mask, bool set) -{ - return yt921x_reg_update_bits(priv, reg, mask, !set ? 0 : mask); -} - -/* Some multi-word registers, like VLANn_CTRL, should be treated as a single - * long register. More specifically, writes to parts of its words won't become - * visible, until the last word is written. - * - * Here we require full read and write operations over these registers to - * eliminate potential issues, although partial reads/writes are also possible. - */ - -static void update_ctrls_unaligned(u32 *lo, u32 *hi, u64 mask, u64 val) -{ - *lo &= ~lower_32_bits(mask); - *hi &= ~upper_32_bits(mask); - *lo |= lower_32_bits(val); - *hi |= upper_32_bits(val); -} - -static int -yt921x_regs_read(struct yt921x_priv *priv, u32 reg, u32 *vals, - unsigned int num_regs) -{ - int res; - - for (unsigned int i = 0; i < num_regs; i++) { - res = yt921x_reg_read(priv, reg + 4 * i, &vals[i]); - if (res) - return res; - } - - return 0; -} - -static int -yt921x_regs_write(struct yt921x_priv *priv, u32 reg, const u32 *vals, - unsigned int num_regs) -{ - int res; - - for (unsigned int i = 0; i < num_regs; i++) { - res = yt921x_reg_write(priv, reg + 4 * i, vals[i]); - if (res) - return res; - } - - return 0; -} - -static int -yt921x_regs_update_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, - const u32 *vals, unsigned int num_regs) -{ - bool changed = false; - u32 vs[4]; - int res; - - BUILD_BUG_ON(num_regs > ARRAY_SIZE(vs)); - - res = yt921x_regs_read(priv, reg, vs, num_regs); - if (res) - return res; - - for (unsigned int i = 0; i < num_regs; i++) { - u32 u = vs[i]; - - u &= ~masks[i]; - u |= vals[i]; - if (u != vs[i]) - changed = true; - - vs[i] = u; - } - - if (!changed) - return 0; - - return yt921x_regs_write(priv, reg, vs, num_regs); -} - -static int -yt921x_regs_clear_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, - unsigned int num_regs) -{ - bool changed = false; - u32 vs[4]; - int res; - - BUILD_BUG_ON(num_regs > ARRAY_SIZE(vs)); - - res = yt921x_regs_read(priv, reg, vs, num_regs); - if (res) - return res; - - for (unsigned int i = 0; i < num_regs; i++) { - u32 u = vs[i]; - - u &= ~masks[i]; - if (u != vs[i]) - changed = true; - - vs[i] = u; - } - - if (!changed) - return 0; - - return yt921x_regs_write(priv, reg, vs, num_regs); -} - -static int -yt921x_reg64_write(struct yt921x_priv *priv, u32 reg, const u32 *vals) -{ - return yt921x_regs_write(priv, reg, vals, 2); -} - -static int -yt921x_reg64_update_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, - const u32 *vals) -{ - return yt921x_regs_update_bits(priv, reg, masks, vals, 2); -} - -static int -yt921x_reg64_clear_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks) -{ - return yt921x_regs_clear_bits(priv, reg, masks, 2); -} - -static int -yt921x_reg96_write(struct yt921x_priv *priv, u32 reg, const u32 *vals) -{ - return yt921x_regs_write(priv, reg, vals, 3); -} - static int yt921x_reg_mdio_read(void *context, u32 reg, u32 *valp) { struct yt921x_reg_mdio *mdio = context; diff --git a/drivers/net/dsa/motorcomm/smi.c b/drivers/net/dsa/motorcomm/smi.c new file mode 100644 index 000000000000..9054896e4cd1 --- /dev/null +++ b/drivers/net/dsa/motorcomm/smi.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2026 David Yang + */ + +#include + +#include "chip.h" +#include "smi.h" + +#define YT921X_POLL_SLEEP_US 10000 +#define YT921X_POLL_TIMEOUT_US 100000 + +int yt921x_reg_read(struct yt921x_priv *priv, u32 reg, u32 *valp) +{ + lockdep_assert_held_once(&priv->reg_lock); + + return priv->reg_ops->read(priv->reg_ctx, reg, valp); +} + +int yt921x_reg_write(struct yt921x_priv *priv, u32 reg, u32 val) +{ + lockdep_assert_held_once(&priv->reg_lock); + + return priv->reg_ops->write(priv->reg_ctx, reg, val); +} + +int yt921x_reg_wait(struct yt921x_priv *priv, u32 reg, u32 mask, u32 *valp) +{ + u32 val; + int res; + int ret; + + ret = read_poll_timeout(yt921x_reg_read, res, + res || (val & mask) == *valp, + YT921X_POLL_SLEEP_US, YT921X_POLL_TIMEOUT_US, + false, priv, reg, &val); + if (ret) + return ret; + if (res) + return res; + + *valp = val; + return 0; +} + +int yt921x_reg_update_bits(struct yt921x_priv *priv, u32 reg, u32 mask, u32 val) +{ + int res; + u32 v; + u32 u; + + res = yt921x_reg_read(priv, reg, &v); + if (res) + return res; + + u = v; + u &= ~mask; + u |= val; + if (u == v) + return 0; + + return yt921x_reg_write(priv, reg, u); +} + +int +yt921x_regs_read(struct yt921x_priv *priv, u32 reg, u32 *vals, + unsigned int num_regs) +{ + int res; + + for (unsigned int i = 0; i < num_regs; i++) { + res = yt921x_reg_read(priv, reg + 4 * i, &vals[i]); + if (res) + return res; + } + + return 0; +} + +int +yt921x_regs_write(struct yt921x_priv *priv, u32 reg, const u32 *vals, + unsigned int num_regs) +{ + int res; + + for (unsigned int i = 0; i < num_regs; i++) { + res = yt921x_reg_write(priv, reg + 4 * i, vals[i]); + if (res) + return res; + } + + return 0; +} + +int +yt921x_regs_update_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, + const u32 *vals, unsigned int num_regs) +{ + bool changed = false; + u32 vs[4]; + int res; + + if (WARN_ON_ONCE(num_regs > ARRAY_SIZE(vs))) + return -EINVAL; + + res = yt921x_regs_read(priv, reg, vs, num_regs); + if (res) + return res; + + for (unsigned int i = 0; i < num_regs; i++) { + u32 u = vs[i]; + + u &= ~masks[i]; + u |= vals[i]; + if (u != vs[i]) + changed = true; + + vs[i] = u; + } + + if (!changed) + return 0; + + return yt921x_regs_write(priv, reg, vs, num_regs); +} + +int +yt921x_regs_clear_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, + unsigned int num_regs) +{ + bool changed = false; + u32 vs[4]; + int res; + + if (WARN_ON_ONCE(num_regs > ARRAY_SIZE(vs))) + return -EINVAL; + + res = yt921x_regs_read(priv, reg, vs, num_regs); + if (res) + return res; + + for (unsigned int i = 0; i < num_regs; i++) { + u32 u = vs[i]; + + u &= ~masks[i]; + if (u != vs[i]) + changed = true; + + vs[i] = u; + } + + if (!changed) + return 0; + + return yt921x_regs_write(priv, reg, vs, num_regs); +} diff --git a/drivers/net/dsa/motorcomm/smi.h b/drivers/net/dsa/motorcomm/smi.h new file mode 100644 index 000000000000..2e956065eb90 --- /dev/null +++ b/drivers/net/dsa/motorcomm/smi.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2026 David Yang + */ + +#ifndef _YT_SMI_H +#define _YT_SMI_H + +#include +#include + +struct yt921x_priv; + +int yt921x_reg_read(struct yt921x_priv *priv, u32 reg, u32 *valp); +int yt921x_reg_write(struct yt921x_priv *priv, u32 reg, u32 val); +int yt921x_reg_wait(struct yt921x_priv *priv, u32 reg, u32 mask, u32 *valp); +int yt921x_reg_update_bits(struct yt921x_priv *priv, u32 reg, u32 mask, + u32 val); + +static inline int +yt921x_reg_set_bits(struct yt921x_priv *priv, u32 reg, u32 mask) +{ + return yt921x_reg_update_bits(priv, reg, 0, mask); +} + +static inline int +yt921x_reg_clear_bits(struct yt921x_priv *priv, u32 reg, u32 mask) +{ + return yt921x_reg_update_bits(priv, reg, mask, 0); +} + +static inline int +yt921x_reg_toggle_bits(struct yt921x_priv *priv, u32 reg, u32 mask, bool set) +{ + return yt921x_reg_update_bits(priv, reg, mask, !set ? 0 : mask); +} + +/* Some multi-word registers, like VLANn_CTRL, should be treated as a single + * long register. More specifically, writes to parts of its words won't become + * visible, until the last word is written. + * + * Here we require full read and write operations over these registers to + * eliminate potential issues, although partial reads/writes are also possible. + */ + +static inline void update_ctrls_unaligned(u32 *lo, u32 *hi, u64 mask, u64 val) +{ + *lo &= ~lower_32_bits(mask); + *hi &= ~upper_32_bits(mask); + *lo |= lower_32_bits(val); + *hi |= upper_32_bits(val); +} + +int yt921x_regs_read(struct yt921x_priv *priv, u32 reg, u32 *vals, + unsigned int num_regs); +int yt921x_regs_write(struct yt921x_priv *priv, u32 reg, const u32 *vals, + unsigned int num_regs); +int yt921x_regs_update_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, + const u32 *vals, unsigned int num_regs); +int yt921x_regs_clear_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, + unsigned int num_regs); + +static inline int +yt921x_reg64_write(struct yt921x_priv *priv, u32 reg, const u32 *vals) +{ + return yt921x_regs_write(priv, reg, vals, 2); +} + +static inline int +yt921x_reg64_update_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks, + const u32 *vals) +{ + return yt921x_regs_update_bits(priv, reg, masks, vals, 2); +} + +static inline int +yt921x_reg64_clear_bits(struct yt921x_priv *priv, u32 reg, const u32 *masks) +{ + return yt921x_regs_clear_bits(priv, reg, masks, 2); +} + +static inline int +yt921x_reg96_write(struct yt921x_priv *priv, u32 reg, const u32 *vals) +{ + return yt921x_regs_write(priv, reg, vals, 3); +} + +#endif -- 2.53.0