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Miller" , Jakub Kicinski , Jiri Pirko , Michal Schmidt , Paolo Abeni , Pasi Vaananen , Petr Oros , Prathosh Satish , Richard Cochran , Simon Horman , Vadim Fedorenko , linux-kernel@vger.kernel.org Subject: [PATCH net-next 0/4] dpll: zl3073x: add PTP clock support Date: Wed, 8 Jul 2026 19:05:23 +0200 Message-ID: <20260708170527.916035-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Add PTP hardware clock support to the zl3073x DPLL driver. Patch 1 adds channel ToD read/write, phase step and delta frequency offset operations as low-level building blocks for PTP callbacks. Patch 2 registers a PTP clock device for each DPLL channel with gettimex64, settime64, adjtime, adjfine and perout callbacks. The adjtime callback splits multi-second adjustments via ToD read-modify-write and sub-second remainders via output phase step. Patch 3 adds a channel TIE (Time Interval Error) write operation for sub-picosecond resolution phase adjustment. Patch 4 adds PTP adjphase and getmaxphase callbacks using TIE write for phase adjustment in AUTO and REFLOCK modes, extends adjtime to handle non-NCO modes via TIE write, and removes the NCO-only gate from PTP clock registration. Ivan Vecera (4): dpll: zl3073x: add channel ToD and phase step operations dpll: zl3073x: add PTP clock support dpll: zl3073x: add channel TIE write operation dpll: zl3073x: add PTP clock adjphase and TIE support drivers/dpll/zl3073x/Kconfig | 6 +- drivers/dpll/zl3073x/chan.c | 307 +++++++++++++++++++ drivers/dpll/zl3073x/chan.h | 48 +++ drivers/dpll/zl3073x/core.c | 8 + drivers/dpll/zl3073x/core.h | 8 + drivers/dpll/zl3073x/dpll.c | 575 +++++++++++++++++++++++++++++++++-- drivers/dpll/zl3073x/dpll.h | 6 + drivers/dpll/zl3073x/regs.h | 56 ++++ 8 files changed, 978 insertions(+), 36 deletions(-) base-commit: 4a13f31a92f35161b499bf29638336885259da78 -- 2.53.0