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[91.94.100.49]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b01ca9ddf0sm2644281e87.50.2026.07.13.01.15.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2026 01:15:12 -0700 (PDT) From: Stacho_P X-Google-Original-From: Stacho_P To: Johan Alvarado Cc: Andrew Lunn , Vladimir Oltean , Alvin Sipraga , Linus Walleij , Russell King , Maxime Chevallier , Luiz Angelo Daros de Luca , Mieczyslaw Nalewaj , netdev@vger.kernel.org, =?UTF-8?q?Stanis=C5=82aw=20Pal?= Subject: Re: [PATCH net-next v6 2/2] net: dsa: realtek: rtl8365mb: add HSGMII support for RTL8367S Date: Mon, 13 Jul 2026 10:14:37 +0200 Message-ID: <20260713081439.18379-1-stacho@venco.com.pl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260711-rtl8367s-sgmii-v6-2-88f7944ddca7@c127.dev> References: <20260711-rtl8367s-sgmii-v6-2-88f7944ddca7@c127.dev> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested this series on a TP-Link Archer AX55 v1: RTL8367S with the SerDes on external interface 1 running HSGMII (2500base-x fixed-link) to the SoC (Qualcomm IPQ5018 stmmac gmac1). Base was OpenWrt's 6.12 kernel; the only adjustment needed was dropping the neg_mode parameter from pcs_get_state() for the older phylink API there. The trunk comes up at 2.5Gbps and passes traffic (all five front ports are behind it, NAT routed through the CPU port plus wire-speed L2 on the switch). Warm reboots and short power cycles bring it up clean every time, no SerDes firmware involved. One observation, quite possibly marginal silicon on my unit: after the device has been powered off for several hours, the first boot brings the link up (2.5Gbps/Full reported, phylink happy) but the data path is heavily degraded - 60-70% packet loss, the surviving packets at normal sub-ms RTT. Re-running the PCS sequence via admin down/up of the CPU port re-rolls the dice (15% and 40% loss on two consecutive attempts) but did not fully recover it; a soft reboot (full re-probe including the chip reset) always restores a clean link. Short power-offs (~a minute) do not reproduce this. For what it's worth, the vendor firmware for this board keeps the DW8051 link-management loop running permanently, which would effectively keep retrying out of exactly such a state. Happy to test follow-up patches if you want to poke at that; I don't think it should block the series - the feature itself works as advertised. Tested-by: Stanisław Pal