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Mon, 13 Jul 2026 01:43:57 -0700 From: Tariq Toukan To: Leon Romanovsky , , "Mark Bloch" , , Saeed Mahameed , Tariq Toukan CC: Alexei Lazar , Alex Vesker , "Andrew Lunn" , Cosmin Ratiu , "David S. Miller" , Dragos Tatulea , "Eric Dumazet" , Feng Liu , Jakub Kicinski , Kees Cook , , Paolo Abeni , Parav Pandit , Shay Drory , Simon Horman , Yevgeny Kliteynik Subject: [PATCH mlx5-next 2/2] net/mlx5: ifc: Add PSP related fields Date: Mon, 13 Jul 2026 11:43:20 +0300 Message-ID: <20260713084320.1015240-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260713084320.1015240-1-tariqt@nvidia.com> References: <20260713084320.1015240-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|BY5PR12MB4258:EE_ X-MS-Office365-Filtering-Correlation-Id: a0b81d54-ab96-4b32-85b0-08dee0baed4b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|23010399003|7416014|376014|1800799024|82310400026|56012099006|11063799006|22082099003|18002099003|3023799007; X-Microsoft-Antispam-Message-Info: UA6M24yFh9uJ63juORNBi9ixMSkvBKGVg4Wu8Sx8/R6/zzDclW2o+73vgdM2XsBSJlHAs3GuORhcZooqX4P4btog+mpjYHaIzZsfAoFM/UYfwXJjFfKS1bJ3qhlIufqAonjwoTjpsooVGQ7ISRUfpy88WyTKs06NqukMuSQJ+Z0CsYW1Gt1QKFQymjyuHM/pIq9o0warJEWG6siQbQlaFpayGMqjZJNpFqfLfYcE23nk3/mAONqgSY72lQA1CD9ny0JDy7M5rLhKRcwo5cptEsSzEcls7WxxCw9MYrZXee1+TqBxcRg+dLh0Cntx6EBWbbl8ZCBZGHxv6GyEbHA1iEXMGqWObce3OzYTfwqzlPhj8uDgFsApTmji6sf6FnW5iaCK09GgChlKs3k17OvI588RM86gBozUq8rzV41JlF5TKJM6K3CGMwO5x0Q1aqprMGvsX5IlpYoWV0CvPdkm3U3TBl0Cp6UHuZ23R9HvHhIeAIsSFjEmONoo9smp9mIDTkJ/k2Upu6Hkgb9AcTKzMZNZK1WDYIcTziJ1r98SftLYfaKG8UpRa1H+g6z3NtlwyD/dHtu5r/Dl7lzbyoWgz2/ZlNvSHNS34X1OY/Jua4mWMRZMsu/IJs7ESySb/UVq6vjpdm8ApdDcXDbbJzfFCfgaIYTzMmbz1Zh5CAZMb1fsWxKSr84O6+/Cif9jgSPv0axgUzpcncodAJvn2kiXKA== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(23010399003)(7416014)(376014)(1800799024)(82310400026)(56012099006)(11063799006)(22082099003)(18002099003)(3023799007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: gQk3VKlzIN2nimeTmCRGosB49ncQ78Bz78rBCJ8lpfDCnvE/u8tXGJ/wjlGTeqNYhbpNDR5CtOjJgA9odoHAoXK3u+fF0Wm7QoyP+3vID3cPFFBtawhLn/k2tN9FJMrOFMdC7+VlMlA6i3/k1XF5sOLzm00UibTjC0M6IcmvxHLcCagNaVQ0DfHAAhkp1/ICQdVgRK4nvf3KlZyyBe51yPmdCB2dKufROcAGXt2tKtImTwqs0w+GXWYYs5XWkjbdnAxRTAbLeT8cSLHkLHlZTg/M96/3V37FgPxuMKdGlQf7gMaOpo27041zSIVUUbndMofFqQ8mecmYFrQgYOGAaeD1p2XEojEFD94LFjfXkEuI+ba00CR+5dGnoojhMoKjbD+U0pM0aC6O0TsuTQtLdTSiIcz8/LYe/AFNINllhtTXvMdZ3YqPNd6WLL4CsSSS X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jul 2026 08:44:18.1430 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a0b81d54-ab96-4b32-85b0-08dee0baed4b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4258 From: Cosmin Ratiu This adds: - misc_parameters_6, containing a few fields for matching PSP headers. As this is the last misc_parameters field defined, retire the old optimization added in commit [1] to not touch the reserved part. - PSP decap action. - PSP SPI header field pointer. [1] commit 667cb65ae5ad ("net/mlx5: Don't store reserved part in FTEs and FGs") Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/fs_core.h | 12 +----------- include/linux/mlx5/device.h | 1 + include/linux/mlx5/mlx5_ifc.h | 17 +++++++++++++++-- 3 files changed, 17 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h index dbaf33b537f7..906584345a02 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h @@ -214,17 +214,7 @@ struct mlx5_ft_underlay_qp { u32 qpn; }; -#define MLX5_FTE_MATCH_PARAM_RESERVED reserved_at_e00 -/* Calculate the fte_match_param length and without the reserved length. - * Make sure the reserved field is the last. - */ -#define MLX5_ST_SZ_DW_MATCH_PARAM \ - ((MLX5_BYTE_OFF(fte_match_param, MLX5_FTE_MATCH_PARAM_RESERVED) / sizeof(u32)) + \ - BUILD_BUG_ON_ZERO(MLX5_ST_SZ_BYTES(fte_match_param) != \ - MLX5_FLD_SZ_BYTES(fte_match_param, \ - MLX5_FTE_MATCH_PARAM_RESERVED) +\ - MLX5_BYTE_OFF(fte_match_param, \ - MLX5_FTE_MATCH_PARAM_RESERVED))) +#define MLX5_ST_SZ_DW_MATCH_PARAM MLX5_ST_SZ_DW(fte_match_param) struct fs_fte_action { int modify_mask; diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index 07a25f264292..8cb321a9fb3d 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -1171,6 +1171,7 @@ enum { MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4, MLX5_MATCH_MISC_PARAMETERS_4 = 1 << 5, MLX5_MATCH_MISC_PARAMETERS_5 = 1 << 6, + MLX5_MATCH_MISC_PARAMETERS_6 = 1 << 7, }; enum { diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 7de01d4f1b5e..cf01922cf69f 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -508,7 +508,8 @@ struct mlx5_ifc_flow_table_prop_layout_bits { u8 reformat_l2_to_l3_audp_tunnel[0x1]; u8 reformat_l3_audp_tunnel_to_l2[0x1]; u8 ignore_flow_level_rtc_valid[0x1]; - u8 reserved_at_70[0x8]; + u8 reserved_at_70[0x7]; + u8 reformat_del_psp_transport[0x1]; u8 log_max_ft_num[0x8]; u8 reserved_at_80[0x10]; @@ -798,6 +799,15 @@ struct mlx5_ifc_fte_match_set_misc5_bits { u8 reserved_at_100[0x100]; }; +struct mlx5_ifc_fte_match_set_misc6_bits { + u8 reserved_at_0[0x1a]; + u8 psp_version[0x4]; + u8 reserved_at_1e[0x2]; + + u8 reserved_at_20[0x1e0]; +}; + + struct mlx5_ifc_cmd_pas_bits { u8 pa_h[0x20]; @@ -2339,7 +2349,7 @@ struct mlx5_ifc_fte_match_param_bits { struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; - u8 reserved_at_e00[0x200]; + struct mlx5_ifc_fte_match_set_misc6_bits misc_parameters_6; }; enum { @@ -6984,6 +6994,7 @@ enum { MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, + MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_6 = 0x7, }; struct mlx5_ifc_query_flow_group_out_bits { @@ -7245,6 +7256,7 @@ enum mlx5_reformat_ctx_type { MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, + MLX5_REFORMAT_TYPE_REMOVE_PSP_TRANSPORT = 0x16, }; struct mlx5_ifc_alloc_packet_reformat_context_in_bits { @@ -7368,6 +7380,7 @@ enum { MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, MLX5_ACTION_IN_FIELD_PSP_SYNDROME = 0x71, + MLX5_ACTION_IN_FIELD_PSP_HEADER_1 = 0x78, }; struct mlx5_ifc_alloc_modify_header_context_out_bits { -- 2.44.0