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[9.244.8.156]) by smtp.gmail.com with ESMTPSA id af79cd13be357-930b545ec44sm418682185a.34.2026.07.18.07.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jul 2026 07:46:14 -0700 (PDT) From: Enzo Adriano To: Junhui Liu Cc: Andre Przywara , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran , Jerome Brunet , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org Subject: Re: [PATCH v2 3/8] clk: sunxi-ng: a733: Add PRCM CCU Date: Sat, 18 Jul 2026 10:46:11 -0400 Message-ID: <20260718144611.1523567-1-enzo.adriano.code@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260711-a733-clk-v2-3-974d188cbe0c@pigmoral.tech> References: <20260711-a733-clk-v2-0-974d188cbe0c@pigmoral.tech> <20260711-a733-clk-v2-3-974d188cbe0c@pigmoral.tech> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Junhui, I re-reviewed patch 3 in v2 after Andre pointed out that my RFC reply lacked a formal tag. I compared the RFC and v2 PRCM drivers and rechecked v2 against the Allwinner A733 User Manual V0.92, chapter 4.2.5. I checked all 11 programmable clock definitions (register offsets and divider/mux/gate fields), all 18 bus-gate definitions, and all 13 reset-map entries. They match the manual. The RFC-to-v2 changes do not invalidate that check: the four R timer clocks move from the MP helper with no M field to the P-only helper while keeping their offsets and P/mux/gate fields unchanged, and the R PWM identifiers are renamed while keeping their offset/mux/gate fields unchanged. I also checked the gate-only BGRs for R-TWD, R-PPU, R-TZMA, and R-CPU-BIST; the manual defines gate bit 0 but no reset bit for those registers, matching v2. Reviewed-by: Enzo Adriano This analysis was done with AI assistance and each finding was checked against the cited sources. Thanks, Enzo