From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19B0A45BD7A for ; Fri, 24 Jul 2026 19:08:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784920118; cv=none; b=NF24NyEPP16DupWKW8mUFaVFjexzPTny7FNPL3nWSEnACW8w9AI91d3Jcuf5Ra5Z4zkB6FgQM6yr/NwFhScUqi1mXUjmtvma9Ckv3D2IMmr/ATeFpehJVEAu2S45G+CiSCp2J7mNducVrnh1jPvMbCBGInrza5I0PeRVaKZsA1w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784920118; c=relaxed/simple; bh=+h32aoU2ErUCEc3ENAJ3GJ6wUlXX5HC8rIWpziFqvNk=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Rnp0YN4eXVmBVtPoUaCJyIem+a8SjVydb4OjXKaSl4NTeGVQbK1wAkDAA7TqFuP6c77PAm1a4veHw6VcVM5up7RH5VaTbCxRONcSZ8D0x/7YpdSqoJzXuR5bPjw5lADjb+iPeDReCNXy0/T4CCvrYL4EIq7kZh2FHicccvnlyqM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=RzFDqgH0; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RzFDqgH0" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-4954aff6088so6889435e9.3 for ; Fri, 24 Jul 2026 12:08:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784920114; x=1785524914; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=MyuwS38PfYwJJi1QJOBh4vgrGD72hR8pS22EH++wjHw=; b=RzFDqgH0hNMS4UrSYoyhXME3PF9zgv50a3xSyHPjWwn1WnXO0d26pqKbGegdJCRQ3g Q5y5qDkY6DhmYlTT77NJ7FmQqAD0DM6YIiRMND3ee8WFd82NVkmtW74HVW+EeZdiRT8J 0LSqTh8D1xi7H9S59YLEPtfFt5re1+2Ppd667GfEddgZpNW0YhkJoCZNl8ZrQrBgJZ/O AFpRhK3Ob+XOc4HdsBQq/b96iTF/NSDw7/9mJSzwjRtdAI1+9BQQBANkkcHJBgjEAP9K KEnW+mMGMiWUp1JfhCJ5+6UPENqtujCBSVBO3S0e5ffWDXeXTtPAMRqp6ELD5+4bG3tR 3dKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784920114; x=1785524914; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=MyuwS38PfYwJJi1QJOBh4vgrGD72hR8pS22EH++wjHw=; b=nggt4FtsHNhAt2vITVPLjhPo9OLGv1o9iiNWGkigjQVqwN+s/k6yAb+EUT+UmRIQyH VoxcBS2/sqZ9vfAiCikeKjca9orbGag5cunQBQF6xItUhRY114sAIJngeBqhnkgSrIhr AB0I/lakOc14gg+vt+211wwHtE0/fWy+LsSMZ7Iq14023JHKj/+qEL6/05yYQgOnTRcH tdc3gdmnhmdFqg3whZokDR7C2Nvqeu/dXZfAR/uIBazd57FZozld9Og+Mh/sZo0wolY9 F7pdZL0bfrw0x/HyWzgTQpGfsXmLT5tVh+PtfM789Vk1q8WPj2qBI9TThPaimjwfnS1r S5dw== X-Forwarded-Encrypted: i=1; AHgh+RqRIBxKFi5JjSO3ExQtR8CwFjSsP9ShSNblPCP2v1JdCsDjAAHWc9qMzrq6uTwr7snYQFerngI=@vger.kernel.org X-Gm-Message-State: AOJu0YzMttjf6BokrUgk9AF2viEf+yIIdL0Pl38XYtoIuXFydG06z+qY 0PDgRO6TieVfMgK2Xicd4fR0BkWwFvbRXuyoilvmzExVjeGkI3XQQL+B1cvAzw== X-Gm-Gg: AR+sD10zioHp4y4+c+jLDbAq89wxFKI5pk8ghAeRXUaZrzQJerUxdCWttkzDRSwCvlw 8yvMbPJWPLISkb4BCN8/sHSPuY4Yj9q+p+1PyCMROSA79y8VtZYXCaeSga/3UeeRZARjzw+vcn2 sW8mbJ9x/V3gwug+7ZdKfFUyqPI+1yi0uYgwj3kDQqE0KZlAywNmXtwNZafoS3A9e+x3K3XQ7mU 2QT0TJLI8kvmZJHIK3EeAzDAGermXUyZhTpwhVx6Qjdtetyf3hFIEPRbZ/x15Wtcz+fTa5WGIxK Z1IK7AqxIy5OTyfF/QOIZdRE9TCe94xFn+gaanQNVlo69McDx2fQvW8BKLrQcm/sYIa6LL9VW23 KwqgLUNMiAleZuFG7HbALkpubY2eMBnbxO0jbWB4pLZfvCvV3N6LQUSlMyZQAC9xqWvyZnzZIQ/ Kiy60ZViB5gcTwHbKeuZCR5w9AN779JKpypC4YtTeRsl656mGN3MXbf3uPfwpv0GB0 X-Received: by 2002:a05:600c:3111:b0:493:cc25:9c0e with SMTP id 5b1f17b1804b1-49573c996e7mr100341005e9.14.1784920114145; Fri, 24 Jul 2026 12:08:34 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-87-3-249-180.retail.telecomitalia.it. [87.3.249.180]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-496b4c8d6b5sm5893755e9.2.2026.07.24.12.08.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 12:08:33 -0700 (PDT) From: Christian Marangi To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Christian Marangi , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next v2 6/6] net: phy: mediatek: add calibration logic for AN7583 Date: Fri, 24 Jul 2026 21:08:09 +0200 Message-ID: <20260724190811.198339-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260724190811.198339-1-ansuelsmth@gmail.com> References: <20260724190811.198339-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Similar to Airoha AN7581 Switch PHY also the Airoha AN7583 SoC requires dedicated calibration and tuneup to make EEE correctly work. Airoha AN7583 differ from AN7581 by having a dedicated table for calibration and additional EEE logic tuneup. Signed-off-by: Christian Marangi --- drivers/net/phy/mediatek/airoha-ge-soc.c | 227 ++++++++++++++++++++++- drivers/net/phy/mediatek/mtk.h | 1 + 2 files changed, 225 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/mediatek/airoha-ge-soc.c b/drivers/net/phy/mediatek/airoha-ge-soc.c index bc487b093cfa..601a64d83365 100644 --- a/drivers/net/phy/mediatek/airoha-ge-soc.c +++ b/drivers/net/phy/mediatek/airoha-ge-soc.c @@ -159,6 +159,106 @@ static u8 an7581_zcal_to_r45ohm[64] = { 52, 50, 48, 46, 44, 42, 40, 39, 36, 35, 32, 32, 30, 28, 27, 25 }; +/* + * 2 chip revision + * TXMR or discrete + * 2 MDI type + * TX AMP test/TX AMP 1G/TX AMP 100M/TX AMP 10M/R50 + * 4 PHY + */ +static int an7583_tx_amp_compensation_tbl[TRANSFORMER_TYPE_MAX][MDI_TYPE_MAX][CALIB_CONST_TYPE_MAX][4] = { + [TXMR] = { + [MDI_0R] = { + [TX_AMP_TEST_A] = { -3, -3, -3, -3 }, + [TX_AMP_TEST_B] = { -3, -3, -3, -3 }, + [TX_AMP_TEST_C] = { -3, -3, -3, -3 }, + [TX_AMP_TEST_D] = { -3, -3, -3, -3 }, + [TX_AMP_1G_A] = { 0, 0, 0, 0 }, + [TX_AMP_1G_B] = { 0, 0, 0, 0 }, + [TX_AMP_1G_C] = { 0, 0, 0, 0 }, + [TX_AMP_1G_D] = { 0, 0, 0, 0 }, + [TX_AMP_100M_A] = { 4, 4, 4, 4 }, + [TX_AMP_100M_B] = { 4, 4, 4, 4 }, + [TX_AMP_10M_A] = { 0, 0, 0, 0 }, + [TX_AMP_10M_B] = { 0, 0, 0, 0 }, + [R50_A] = { 4, 4, 0, 0 }, + [R50_B] = { 4, 4, 0, 0 }, + [R50_C] = { 5, 5, 3, 4 }, + [R50_D] = { 4, 4, 4, 0 }, + }, + [MDI_5R] = { + [TX_AMP_TEST_A] = { -3, -3, -3, -3 }, + [TX_AMP_TEST_B] = { -3, -3, -3, -3 }, + [TX_AMP_TEST_C] = { -3, -3, -3, -3 }, + [TX_AMP_TEST_D] = { -3, -3, -3, -3 }, + [TX_AMP_1G_A] = { 0, 0, 0, 0 }, + [TX_AMP_1G_B] = { 0, 0, 0, 0 }, + [TX_AMP_1G_C] = { 0, 0, 0, 0 }, + [TX_AMP_1G_D] = { 0, 0, 0, 0 }, + [TX_AMP_100M_A] = { 4, 4, 4, 4 }, + [TX_AMP_100M_B] = { 4, 4, 4, 4 }, + [TX_AMP_10M_A] = { 0, 0, 0, 0 }, + [TX_AMP_10M_B] = { 0, 0, 0, 0 }, + [R50_A] = { -4, -4, -4, -4 }, + [R50_B] = { -4, -4, -4, -4 }, + [R50_C] = { -2, -2, -2, -2 }, + [R50_D] = { -3, -3, -2, -2 }, + }, + }, + [DISCRETE] = { + [MDI_0R] = { + [TX_AMP_TEST_A] = { -3, -3, -3, -3 }, + [TX_AMP_TEST_B] = { -3, -3, -3, -3 }, + [TX_AMP_TEST_C] = { -3, -3, -3, -3 }, + [TX_AMP_TEST_D] = { -3, -3, -3, -3 }, + [TX_AMP_1G_A] = { 0, 0, 0, 0 }, + [TX_AMP_1G_B] = { 0, 0, 0, 0 }, + [TX_AMP_1G_C] = { 0, 0, 0, 0 }, + [TX_AMP_1G_D] = { 0, 0, 0, 0 }, + [TX_AMP_100M_A] = { 4, 4, 4, 4 }, + [TX_AMP_100M_B] = { 4, 4, 4, 4 }, + [TX_AMP_10M_A] = { 0, 0, 0, 0 }, + [TX_AMP_10M_B] = { 0, 0, 0, 0 }, + [R50_A] = { 4, 4, 4, 4 }, + [R50_B] = { 4, 4, 4, 4 }, + [R50_C] = { 6, 6, 6, 6 }, + [R50_D] = { 4, 4, 4, 4 }, + }, + [MDI_5R] = { + [TX_AMP_TEST_A] = { -3, -3, -3, -3 }, + [TX_AMP_TEST_B] = { -3, -3, -3, -3 }, + [TX_AMP_TEST_C] = { -3, -3, -3, -3 }, + [TX_AMP_TEST_D] = { -3, -3, -3, -3 }, + [TX_AMP_1G_A] = { 0, 0, 0, 0 }, + [TX_AMP_1G_B] = { 0, 0, 0, 0 }, + [TX_AMP_1G_C] = { 0, 0, 0, 0 }, + [TX_AMP_1G_D] = { 0, 0, 0, 0 }, + [TX_AMP_100M_A] = { 4, 4, 4, 4 }, + [TX_AMP_100M_B] = { 4, 4, 4, 4 }, + [TX_AMP_10M_A] = { 0, 0, 0, 0 }, + [TX_AMP_10M_B] = { 0, 0, 0, 0 }, + [R50_A] = { 0, 0, 0, 0 }, + [R50_B] = { 0, 0, 0, 0 }, + [R50_C] = { 0, 0, 0, 0 }, + [R50_D] = { 0, 0, 0, 0 }, + }, + }, +}; + +static u8 an7583_zcal_to_r50ohm_0R[64] = { + 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, + 127, 127, 127, 122, 118, 114, 110, 106, 102, 98, 96, 92, 88, 85, 82, 80, + 76, 72, 70, 68, 64, 62, 60, 57, 55, 52, 50, 48, 46, 44, 41, 40, + 38, 36, 33, 32, 30, 28, 26, 24, 24, 22, 20, 18, 16, 16, 14, 12, +}; + +static u8 an7583_zcal_to_r50ohm_5R[64] = { + 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, + 127, 127, 127, 127, 127, 127, 127, 127, 127, 124, 120, 116, 112, 110, 106, 102, + 99, 96, 93, 90, 88, 84, 81, 79, 76, 73, 71, 68, 66, 64, 61, 59, + 56, 54, 52, 50, 48, 46, 44, 42, 40, 39, 37, 36, 33, 32, 31, 29, +}; + static int airoha_cal_cycle(struct phy_device *phydev, int devad, u32 regnum, u16 mask, u16 cal_val) { @@ -766,8 +866,9 @@ static int airoha_rx_offset_cal_sw(struct phy_device *phydev) phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0x171, BIT(8) | BIT(7)); - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG6, - 0x1); + if (phydev->drv->phy_id == AIROHA_GPHY_ID_AN7581) + phy_write_mmd(phydev, MDIO_MMD_VEND1, + MTK_PHY_RG_ANA_CAL_RG6, 0x1); return 0; } @@ -1540,8 +1641,126 @@ static int an7581_phy_led_polarity_set(struct phy_device *phydev, int index, static int an7583_phy_config_init(struct phy_device *phydev) { + struct airoha_socphy_shared *shared = phy_package_get_priv(phydev); + struct phy_device *phydev_p0; + u8 phy_offset; + int ret; + /* BMCR_PDOWN is enabled by default */ - return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); + phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); + + phydev_p0 = shared->phydev_p0; + phy_offset = phydev->mdio.addr - phydev_p0->mdio.addr; + + /* FIXME: Read SoC MDI Resister Type if available or default to 5R */ + shared->mdi_resister_type = MDI_5R; + + shared->mdi_resister_type = MDI_5R; + if (shared->mdi_resister_type == MDI_0R) + shared->r50_cal_tbl = an7583_zcal_to_r50ohm_0R; + if (shared->mdi_resister_type == MDI_5R) + shared->r50_cal_tbl = an7583_zcal_to_r50ohm_5R; + shared->tx_amp_compensation_tbl = &an7583_tx_amp_compensation_tbl; + + ret = airoha_phy_calib(phydev); + if (ret) + return ret; + + ret = airoha_phy_auto_select_transformer(phydev); + if (ret) + return ret; + + ret = airoha_phy_tx_amp_compensation(phydev); + if (ret) + return ret; + + /* Enable Idle Mode Power Setting */ + if (phy_offset == 0) { + phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x268, 0x07F1); + phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x703, 0x3111); + phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x271, 0x3C24); + phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x701, 0x1023); + } + + if (shared->transformer_type[phy_offset] == TXMR) { + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x23, 0x0881); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x24, 0x0881); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x25, 0x0881); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x26, 0x0881); + + if (shared->mdi_resister_type == MDI_0R) + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x05, 0x0205); + else + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x05, 0x0200); + } else { + if (shared->mdi_resister_type == MDI_0R) { + /* RX setting for 5R_TXMR before AN setting */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xe7, 0x6666); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xe9, 0x0003); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xfe, 0x0006); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xe6, 0x1111); + /* 100M sharp */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x23, 0x0c86); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x24, 0x0c86); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x25, 0x0c86); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x26, 0x0c86); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01, 0x01cb); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x02, 0x01c2); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x03, 0x0108); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x04, 0x0211); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x05, 0x0205); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x06, 0x0387); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x07, 0x03ce); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x08, 0x03c8); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0b, 0x0005); + } else { + /* 100M sharp */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x23, 0x0886); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x24, 0x0886); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x25, 0x0886); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x26, 0x0886); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x00, 0x0195); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01, 0x01cb); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x02, 0x01c2); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x03, 0x0108); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x04, 0x0211); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x05, 0x0205); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x06, 0x0387); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x07, 0x03ce); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x08, 0x03c3); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0a, 0x0010); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0b, 0x0005); + } + } + + /* RX Setting */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x3c, 0xc000); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x3d, 0x0000); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x3e, 0xc000); + + /* EEE setting */ + phy_write_mmd(phydev, MDIO_MMD_AN, 0x3c, 0x0000); + + /* 10M settings */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x1a3, 0x00d2); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x1a4, 0x010e); + phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x27b, 0x1177); + phy_write_mmd(phydev, MDIO_MMD_VEND2, 0x27c, 0x0808); + + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); + __phy_write(phydev, 0x14, 0x190); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_1); + __phy_write(phydev, 0x14, 0x3a18); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + + phy_write(phydev, 0x9, 0x0600); + + /* EEE keep only Pair A ON */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x630, 0x006E); + + return 0; } static struct phy_driver mtk_socphy_driver[] = { @@ -1572,6 +1791,8 @@ static struct phy_driver mtk_socphy_driver[] = { .led_hw_control_set = mt798x_phy_led_hw_control_set, .led_hw_control_get = mt798x_phy_led_hw_control_get, .led_polarity_set = an7581_phy_led_polarity_set, + .read_page = mtk_phy_read_page, + .write_page = mtk_phy_write_page, }, }; diff --git a/drivers/net/phy/mediatek/mtk.h b/drivers/net/phy/mediatek/mtk.h index c690aaf38124..cd9d4c5550c3 100644 --- a/drivers/net/phy/mediatek/mtk.h +++ b/drivers/net/phy/mediatek/mtk.h @@ -13,6 +13,7 @@ #define MTK_EXT_PAGE_ACCESS 0x1f #define MTK_PHY_PAGE_EXTENDED_1 0x0001 +#define MTK_PHY_PAGE_EXTENDED_3 0x0003 #define MTK_PHY_PAGE_STANDARD 0x0000 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 -- 2.53.0