From: Michael Gur <michaelgur@nvidia.com>
To: jgg@ziepe.ca, leon@kernel.org
Cc: linux-rdma@vger.kernel.org, netdev@vger.kernel.org,
Edward Srouji <edwards@nvidia.com>,
Yishai Hadas <yishaih@nvidia.com>,
Michael Gur <michaelgur@nvidia.com>,
Saeed Mahameed <saeedm@nvidia.com>,
Tariq Toukan <tariqt@nvidia.com>, Mark Bloch <mbloch@nvidia.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH rdma-next 07/15] mlx5: Move RO setting helper to core and consolidate mlx5 consumers
Date: Sun, 26 Jul 2026 12:29:21 +0300 [thread overview]
Message-ID: <20260726092943.2880176-8-michaelgur@nvidia.com> (raw)
In-Reply-To: <20260726092943.2880176-1-michaelgur@nvidia.com>
Move mlx5e_mkey_set_relaxed_ordering() from en_common.c to core/mr.c
as mlx5_core_mkey_set_relaxed_ordering() and export it. The helper
centralizes the cap gating for order_write_after_write and
pci_relaxed_ordered_read so each consumer no longer has to open-code
the same dance.
Switch the static MR creation path (set_mkc_access_pd_addr_fields)
and the UMR access-modify path (mlx5r_umr_set_access_flags) over to
the new helper. Both call it inside the IB_ACCESS_RELAXED_ORDERING
gate, preserving their existing conditional semantics: RO bits are
only written when the caller actually requested RO. The Ethernet
path already uses the helper unconditionally on every internal mkey
it creates.
Consolidating onto the helper has two benefits beyond the
deduplication itself:
* pcie_relaxed_ordering_enabled() is now invoked only when the
caller requests RO, avoiding pci_lock contention on every MR
registration.
* Reorder the inner AND so the cheap cap check short-circuits the
slow pcie_relaxed_ordering_enabled() call on HW that lacks the
relaxed_ordering_read_pci_enabled cap.
Reviewed-by: Yishai Hadas <yishaih@nvidia.com>
Signed-off-by: Michael Gur <michaelgur@nvidia.com>
---
drivers/infiniband/hw/mlx5/mr.c | 12 ++---------
drivers/infiniband/hw/mlx5/umr.c | 10 +++------
drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 -
.../ethernet/mellanox/mlx5/core/en_common.c | 13 +-----------
.../net/ethernet/mellanox/mlx5/core/en_main.c | 4 ++--
drivers/net/ethernet/mellanox/mlx5/core/mr.c | 21 +++++++++++++++++++
include/linux/mlx5/driver.h | 1 +
7 files changed, 30 insertions(+), 32 deletions(-)
diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c
index 53bc844a7fc8..683099333563 100644
--- a/drivers/infiniband/hw/mlx5/mr.c
+++ b/drivers/infiniband/hw/mlx5/mr.c
@@ -71,16 +71,8 @@ static void set_mkc_access_pd_addr_fields(void *mkc, int acc, u64 start_addr,
MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE));
MLX5_SET(mkc, mkc, lr, 1);
- if (acc & IB_ACCESS_RELAXED_ORDERING) {
- if (MLX5_CAP_GEN(dev->mdev, mkc_order_write_after_write_ro))
- MLX5_SET(mkc, mkc, order_write_after_write, 1);
-
- if (MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read) ||
- (MLX5_CAP_GEN(dev->mdev,
- relaxed_ordering_read_pci_enabled) &&
- pcie_relaxed_ordering_enabled(dev->mdev->pdev)))
- MLX5_SET(mkc, mkc, pci_relaxed_ordered_read, 1);
- }
+ if (acc & IB_ACCESS_RELAXED_ORDERING)
+ mlx5_core_mkey_set_relaxed_ordering(dev->mdev, mkc);
MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
MLX5_SET(mkc, mkc, qpn, 0xffffff);
diff --git a/drivers/infiniband/hw/mlx5/umr.c b/drivers/infiniband/hw/mlx5/umr.c
index 05ab0a32ded6..b0799f86994d 100644
--- a/drivers/infiniband/hw/mlx5/umr.c
+++ b/drivers/infiniband/hw/mlx5/umr.c
@@ -445,18 +445,14 @@ static void mlx5r_umr_set_access_flags(struct mlx5_ib_dev *dev,
struct mlx5_mkey_seg *seg,
unsigned int access_flags)
{
- bool ro_read = (access_flags & IB_ACCESS_RELAXED_ORDERING) &&
- (MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read) ||
- pcie_relaxed_ordering_enabled(dev->mdev->pdev));
-
MLX5_SET(mkc, seg, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
MLX5_SET(mkc, seg, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
MLX5_SET(mkc, seg, rr, !!(access_flags & IB_ACCESS_REMOTE_READ));
MLX5_SET(mkc, seg, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE));
MLX5_SET(mkc, seg, lr, 1);
- MLX5_SET(mkc, seg, order_write_after_write,
- !!(access_flags & IB_ACCESS_RELAXED_ORDERING));
- MLX5_SET(mkc, seg, pci_relaxed_ordered_read, ro_read);
+
+ if (access_flags & IB_ACCESS_RELAXED_ORDERING)
+ mlx5_core_mkey_set_relaxed_ordering(dev->mdev, seg);
}
int mlx5r_umr_rereg_pd_access(struct mlx5_ib_mr *mr, struct ib_pd *pd,
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h
index 2270e2e550dd..4a0ef2757981 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h
@@ -1192,7 +1192,6 @@ int mlx5e_modify_tirs_lb(struct mlx5_core_dev *mdev, bool enable_uc_lb,
bool enable_mc_lb);
int mlx5e_refresh_tirs(struct mlx5_core_dev *mdev, bool enable_uc_lb,
bool enable_mc_lb);
-void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
/* common netdev helpers */
void mlx5e_create_q_counters(struct mlx5e_priv *priv);
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c
index 2dbcf6673916..62b40a73ba77 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c
@@ -38,17 +38,6 @@
* Global resources are common to all the netdevices created on the same nic.
*/
-void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc)
-{
- bool ro_write = MLX5_CAP_GEN(mdev, mkc_order_write_after_write_ro);
- bool ro_read = MLX5_CAP_GEN(mdev, pci_relaxed_ordered_read) ||
- (pcie_relaxed_ordering_enabled(mdev->pdev) &&
- MLX5_CAP_GEN(mdev, relaxed_ordering_read_pci_enabled));
-
- MLX5_SET(mkc, mkc, pci_relaxed_ordered_read, ro_read);
- MLX5_SET(mkc, mkc, order_write_after_write, ro_write);
-}
-
int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey)
{
int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
@@ -64,7 +53,7 @@ int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey)
MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);
MLX5_SET(mkc, mkc, lw, 1);
MLX5_SET(mkc, mkc, lr, 1);
- mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
+ mlx5_core_mkey_set_relaxed_ordering(mdev, mkc);
MLX5_SET(mkc, mkc, pd, pdn);
MLX5_SET(mkc, mkc, length64, 1);
MLX5_SET(mkc, mkc, qpn, 0xffffff);
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
index 775f0c6e55c9..6a486e6fd9cb 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
@@ -462,7 +462,7 @@ static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
MLX5_SET(mkc, mkc, lw, 1);
MLX5_SET(mkc, mkc, lr, 1);
MLX5_SET(mkc, mkc, access_mode_1_0, mlx5e_mpwrq_access_mode(umr_mode));
- mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
+ mlx5_core_mkey_set_relaxed_ordering(mdev, mkc);
MLX5_SET(mkc, mkc, qpn, 0xffffff);
MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
MLX5_SET64(mkc, mkc, len, npages << page_shift);
@@ -801,7 +801,7 @@ static int mlx5e_create_rq_hd_mkey(struct mlx5_core_dev *mdev,
MLX5_SET(mkc, mkc, lw, 1);
MLX5_SET(mkc, mkc, lr, 1);
MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
- mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
+ mlx5_core_mkey_set_relaxed_ordering(mdev, mkc);
MLX5_SET(mkc, mkc, qpn, 0xffffff);
MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
MLX5_SET64(mkc, mkc, len, shampo->hd_buf_size);
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mr.c b/drivers/net/ethernet/mellanox/mlx5/core/mr.c
index 678f0be81375..c615a6ea1a04 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/mr.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/mr.c
@@ -35,6 +35,27 @@
#include <linux/mlx5/qp.h>
#include "mlx5_core.h"
+/**
+ * mlx5_core_mkey_set_relaxed_ordering - Set RO flags in mkey context
+ * @dev: MLX5 core device
+ * @mkc: Memory key context buffer
+ *
+ * Sets order_write_after_write and pci_relaxed_ordered_read in @mkc
+ * based on device caps. Call when creating or modifying a memory key to have
+ * relaxed ordering.
+ */
+void mlx5_core_mkey_set_relaxed_ordering(struct mlx5_core_dev *dev, void *mkc)
+{
+ bool ro_write = MLX5_CAP_GEN(dev, mkc_order_write_after_write_ro);
+ bool ro_read = MLX5_CAP_GEN(dev, pci_relaxed_ordered_read) ||
+ (MLX5_CAP_GEN(dev, relaxed_ordering_read_pci_enabled) &&
+ pcie_relaxed_ordering_enabled(dev->pdev));
+
+ MLX5_SET(mkc, mkc, pci_relaxed_ordered_read, ro_read);
+ MLX5_SET(mkc, mkc, order_write_after_write, ro_write);
+}
+EXPORT_SYMBOL(mlx5_core_mkey_set_relaxed_ordering);
+
int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
int inlen)
{
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index b1871c0821d0..bc449b26be56 100644
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -1035,6 +1035,7 @@ void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
struct mlx5_frag_buf *buf, int node);
void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
+void mlx5_core_mkey_set_relaxed_ordering(struct mlx5_core_dev *dev, void *mkc);
int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
int inlen);
int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
--
2.52.0
next prev parent reply other threads:[~2026-07-26 9:30 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-26 9:29 [PATCH rdma-next 00/15] RDMA: Support HW requiring relaxed ordering and add Unordered access flag Michael Gur
2026-07-26 9:29 ` [PATCH rdma-next 01/15] RDMA/mlx5: Allow optional access flags in DM registration Michael Gur
2026-07-26 9:29 ` [PATCH rdma-next 02/15] RDMA/mlx5: Allow optional access flags in DEVX UMEM registration Michael Gur
2026-07-26 9:29 ` [PATCH rdma-next 03/15] RDMA/core: Allow optional access flags in dmabuf reg ioctl Michael Gur
2026-07-26 9:29 ` [PATCH rdma-next 04/15] RDMA/core: Allow optional access flags in reg mr ioctl Michael Gur
2026-07-26 9:29 ` [PATCH rdma-next 05/15] mlx5: Rename IFC bits of relaxed ordering fields Michael Gur
2026-07-26 9:29 ` [PATCH rdma-next 06/15] net/mlx5: Add IFC bits for new ordering caps Michael Gur
2026-07-26 9:29 ` Michael Gur [this message]
2026-07-26 9:29 ` [PATCH rdma-next 08/15] net/mlx5: Enable relaxed ordering on resource dump mkey Michael Gur
2026-07-26 9:29 ` [PATCH rdma-next 09/15] vfio/mlx5: Enable relaxed ordering on the live migration data mkey Michael Gur
2026-07-26 9:29 ` [PATCH rdma-next 10/15] RDMA/mlx5: Enable relaxed ordering on ODP null mkey Michael Gur
2026-07-26 9:29 ` [PATCH rdma-next 11/15] RDMA/mlx5: Enable relaxed ordering on Memory Window mkey on strict-RO HW Michael Gur
2026-07-26 9:29 ` [PATCH rdma-next 12/15] RDMA/mlx5: Converge UMR access-flag cap checks Michael Gur
2026-07-26 9:29 ` [PATCH rdma-next 13/15] RDMA/uverbs: Add new Unordered MR access flag Michael Gur
2026-07-26 9:29 ` [PATCH rdma-next 14/15] RDMA/mlx5: Support new Unordered " Michael Gur
2026-07-26 9:29 ` [PATCH rdma-next 15/15] RDMA/mlx5: Enforce relaxed ordering when HW requires it Michael Gur
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