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Mon, 27 Jul 2026 07:11:32 -0700 (PDT) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-314bc44cb92sm53438677eec.13.2026.07.27.07.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jul 2026 07:11:32 -0700 (PDT) From: Imran Shaik Subject: [PATCH 0/6] Add support for Qualcomm TSCSS hardware Date: Mon, 27 Jul 2026 19:40:56 +0530 Message-Id: <20260727-tscss-v1-0-beed14e72510@oss.qualcomm.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAPBmZ2oC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDcwNT3ZLi5OJiXRMTwxQLE5Nkw9RUcyWg2oKi1LTMCrA50bG1tQDCDfz 9VwAAAA== X-Change-ID: 20260705-tscss-441d844c1ee7 To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bjorn Andersson , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Imran Shaik X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI3MDEzNSBTYWx0ZWRfX4KwZRcIECueL EDNElrfX8+CYYEgKjlHGZkJtPb1oW3H6Yg0PXw3oBSP1t7FbaO6a9AvPCgF5B0PuHxP2N+xpjqf pTqrNYD6MZYOXAhzPbnYRLYZv6Fo5Wk= X-Authority-Analysis: v=2.4 cv=UYBhjqSN c=1 sm=1 tr=0 ts=6a676716 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=CuubQGV2Owguao5XfqgA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-GUID: ctTp6qrhRuiqzkoogU1WYlo6-xZ0b7rF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI3MDEzNSBTYWx0ZWRfXwKC4FyjB1rNu p/Z30xbCuFc8A3PHrLW/KobyTghiQ8jD+db2J5FtQFwCUbvKwRsTNZS3ESaE3w4ZIomaiwjGoIG YfoOzBTHJW7UptpbKL7MGnv04FAP6E8w12Lcvv+ACfmVF6Cf4oBF9nUJeALn0EdTOg4L7X72Q9y WloeBpDN6k6Y/2Mv5cSejLZJX6eRW+QAi5KSnwIe8Dark8izc9z1Yl75VhgL0H9f0KPRBx+x/Fi w/nxAI/e/cRya3hhPJw1024KkFKMy3ZHQIAZ3RmdHRoqwmkk3iV/Q9N+hegeeNHhH+vYqEkGqWz K7tAbINAy9KBNFky43i844XMWslP305X5U758LFpPi5CGdHi4Tl3BZ+R3GiQ4skfVBebeUpzq1P AHdOmr7fVC/giI/H2Rjn5j/Ih+N5iWKqWYyUqf3giAjvwmaW/jEiY3WS2ZC1GFyKas/nNNXW7DW AN+cJ6NJOOhd+jjOWrQ== X-Proofpoint-ORIG-GUID: ctTp6qrhRuiqzkoogU1WYlo6-xZ0b7rF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-27_04,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 phishscore=0 adultscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607270135 This series introduces support for the Qualcomm Timestamp Counter Subsystem (TSCSS) hardware, a time synchronization subsystem present on Qualcomm Lemans, Monaco and QDU1000 SoCs. TSCSS is composed of two main hardware blocks: - Timestamp Counter (TSC): a free-running hardware counter that provides continuous timekeeping for the SoC, and is functional with a GCC TSC AHB config clock and a global counter clock. The TSC counter resolution and supported functionalities vary across SoC variants. - Event Timestamp Unit (ETU): an optional block that captures TSC counter timestamps against external hardware events. Each ETU slice binds a slice identifier to an external event selector, and the ETU additionally requires its own clock, pinctrl along with either a per-slice interrupt (QDU1000) or a single summary interrupt across all ETU slices (Lemans and Monaco). +------------------------------------------------+ +------------------+ | Global clock controller - TSC AHB/CNTR/ETU CLK | | EVENT_IN[0:15] | +------------------------------------------------+ +------------------+ | | v v +----------------------------------------------------------------------+ | Timestamp Counter Subsystem (TSCSS) | | | | +----------------------------------------------+ | | +------------+ | Event Timestamp Unit (ETU) | | | | Timestamp | | 0x01C90000-0x01C9FFFF | | | | Counter | | +------------------------------------------+ | | | | (TSC) | | | ETU Slices | | | | | | | | [Slice 0] [Slice 1] [...] [Slice 15] | | | | | 0x1C80000 | | | 0x1C90000 0x1C91000 0x1C9F000 | | | | +------------+ | | | | | | | +-----------+------------------------------+ | | | +-------------|--------------------+-----------+ | | | | | +---------------------------------|--------------------|---------------+ | | v v +----------------------------------------+ | per-slice IRQ (OR) summary IRQ | | (QDU1000) (Lemans) | +----------------------------------------+ | v +-----------------------------+ | Interrupt Controller | +-----------------------------+ The address offsets shown in the diagram above are specific to Qualcomm Lemans SoC. This series currently covers only the TSC block driver functionality; ETU driver support will follow in a later series. Signed-off-by: Imran Shaik --- Imran Shaik (6): dt-bindings: ptp: Document the TSCSS on Qualcomm Lemans and Monaco SoCs dt-bindings: ptp: Document TSCSS hardware on Qualcomm QDU1000 SoC ptp: qcom: Add PTP driver for the Qualcomm TSC hardware arm64: defconfig: Enable Qualcomm TSC driver arm64: dts: qcom: lemans: Add support for TSCSS node arm64: dts: qcom: qdu1000: Add support for TSCSS node .../devicetree/bindings/ptp/qcom,lemans-tscss.yaml | 198 ++++++++++ .../bindings/ptp/qcom,qdu1000-tscss.yaml | 187 ++++++++++ arch/arm64/boot/dts/qcom/lemans.dtsi | 11 + arch/arm64/boot/dts/qcom/qdu1000.dtsi | 11 + arch/arm64/configs/defconfig | 1 + drivers/ptp/Kconfig | 10 + drivers/ptp/Makefile | 1 + drivers/ptp/ptp_qcom_tsc.c | 413 +++++++++++++++++++++ 8 files changed, 832 insertions(+) --- base-commit: c5e32e86ca02b003f86e095d379b38148999293d change-id: 20260705-tscss-441d844c1ee7 Best regards, -- Imran Shaik